Abstract: A developed impact mark analysis apparatus includes: an image acquisition unit configured to obtain at least one first image by photographing impact marks that are developed, and to obtain a second image of impact marks at a crime scene that are developed from evidence at the crime scene; an outliner configured to outline the at least one first image to obtain at least one first outline image, and to outline the second image to obtain a second outline image; a database configured to store the first outline image corresponding to related tool characteristic information; a matching unit configured to search the database for the first outline image determined to be similar to the second outline image and match them with each other; a display unit; and a user input unit.

Abstract: Provided herein may be a memory controller and a memory system including the same. The memory controller includes a scanning period controller configured to reset, whenever scanning points sequentially arrive, access information indicating whether each of a plurality of pages is accessed, and set a scanning interval for each of the pages between the scanning points for the page based on an attribute of the page, an attribute determiner configured to determine, as a hot page or a cold page, the attribute of each of the pages based on an access interval for the page from the first scanning point among the scanning points for the page to time at which access to data stored in the page is requested, and a memory allocator configured to control first and second memory devices based on the attributes of the pages.

Abstract: A computing system comprises a memory and a controller, and the controller is configured to store a first type of data and a second type of data in the memory, to divide the first type of data into a first part and a second part, to generate parity information on the first part and to store the parity information in the memory, and a refresh interval of a region of the memory where the first type of data is stored is larger than a refresh interval of a region of the memory where the second type of data is stored.

Abstract: A memory controller includes: a data separator configured to separate host write data into upper data and lower data; an address generator configured to generate a first address and a second address based on a host address; a command generator configured to generate one or more first commands for writing the upper data into a first storage region that is selected based on the first address in a memory, and one or more second commands for writing the lower data into a second storage region that is selected based on the second address in the memory; and a control block configured to control the address generator and the command generator to make a difference in power consumption between the first storage region and the second storage region.

Abstract: A memory system includes a memory device and a controller. The memory device includes plural storage regions including plural non-volatile memory cells. The plural storage regions have a different data input/output speed. The controller is coupled to the memory device via at least one data path. The controller performs a readahead operation in response to a read request input from an external device, determines a data attribute regarding readahead data, obtained by the readahead operation, based on a time difference between reception of the read request and completion of the readahead operation, and stores the readahead data in one of the plural storage regions based on the data attribute.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory controller may include an attribute determiner configured to determine an attribute of each of a plurality of pages included in a first external device to indicate one of a hot page and a cold page, based on an access interval which is an interval from a time at which data is stored in each of the pages to a time at which access to the data is requested, a page analyzer configured to determine a ratio of hot pages having a hot page attribute to the plurality of pages, and a memory allocator configured to control one of the first external device and the second external device to store therein externally provided data based on the ratio of hot pages.

Abstract: Provided herein may be a memory controller and a memory system including the same. The memory controller includes a scanning period controller configured to reset, whenever scanning points sequentially arrive, access information indicating whether each of a plurality of pages is accessed, and set a scanning interval for each of the pages between the scanning points for the page based on an attribute of the page, an attribute determiner configured to determine, as a hot page or a cold page, the attribute of each of the pages based on an access interval for the page from the first scanning point among the scanning points for the page to time at which access to data stored in the page is requested, and a memory allocator configured to control first and second memory devices based on the attributes of the pages.

Abstract: An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

Abstract: A memory system includes a memory device and a controller. The memory device includes plural storage regions including plural non-volatile memory cells. The plural storage regions have a different data input/output speed. The controller is coupled to the memory device via at least one data path. The controller performs a readahead operation in response to a read request input from an external device, determines a data attribute regarding readahead data, obtained by the readahead operation, based on a time difference between reception of the read request and completion of the readahead operation, and stores the readahead data in one of the plural storage regions based on the data attribute.

Abstract: A data center includes a refrigerant induction pipe surrounding one or more regions of the data center, a refrigerant supply device suitable for supplying a refrigerant to the refrigerant induction pipe, the refrigerant having a vaporization temperature corresponding to a pseudo cryogenic temperature, a plurality of racks disposed in the one or more regions, and a plurality of rotating devices, each rotating device being suitable for rotating a corresponding one of the plurality of racks.

Abstract: An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

Abstract: A main memory device includes a first memory device; and a second memory device having an access latency different from that of the first memory device. The first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region.

Abstract: A cooling system for efficiently cooling large-scale data storage devices embedded in a vehicle, and a smart vehicle including the same are disclosed. The storage device cooling system includes a storage housing section located at a ceiling-mounted structure of a vehicle, provided with an indoor space thereof in which a plurality of storage devices is kept and an opening/closing device configured to open or close the indoor space, a sensing circuit configured to detect a temperature of the indoor space, and an opening/closing controller configured to control operations of the opening/closing device in response to the temperature detected by the sensing circuit.

Abstract: A memory device includes a data storage region and a spare column remap storage. The data storage region includes a plurality of sub-arrays, and each of the plurality of sub-arrays has a plurality of main columns and a plurality of spare columns. The spare column remap storage includes a plurality of storage units storing column address information of a repaired main column of one of the plurality of sub-arrays and address information of a repaired main column of another of the plurality of sub-arrays into at least one of the plurality of storage units included in the spare column remap storage.

Abstract: A memory module may include: a plurality of stacked memory chips; a memory controller; and an interposer connected between the plurality of memory chips and the memory controller.

Abstract: A semiconductor module includes a module board, an interposer on the module board, and a processing device and a memory stack that are disposed side by side on the interposer, wherein the memory stack includes a base die, and a memory die on the base die, wherein the memory die includes an outer bank region, a central TSV region, first and second inner bank regions, and a first non-central TSV region, wherein the central TSV region is disposed between the outer bank region and the second inner bank region, and the first non-central TSV region is disposed between the first inner bank region and the second inner bank region.

Abstract: An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

Abstract: A memory device includes a data storage region and a spare column remap storage. The data storage region includes a plurality of sub-arrays, and each of the plurality of sub-arrays has a plurality of main columns and a plurality of spare columns. The spare column remap storage includes a plurality of storage units storing column address information of a repaired main column of one of the plurality of sub-arrays and address information of a repaired main column of another of the plurality of sub-arrays into at least one of the plurality of storage units included in the spare column remap storage.

Abstract: An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

Abstract: A memory device includes a data storage region and a spare column remap storage. The data storage region includes a plurality of sub-arrays, each of which has a plurality of main columns and a plurality of spare columns. The spare column remap storage includes a plurality of storage units storing address information of the main columns repaired using the plurality of spare columns. At least one of the plurality of storage units included in the spare column remap storage is provided to store address information of the main column repaired in one of the plurality of sub-arrays and address information of the main column repaired in another of the plurality of sub-arrays.