Abstract: A semiconductor device includes a substrate including a cell array region and a peripheral circuit region. The semiconductor device further includes a cell array disposed in the cell array region and including a plurality of cell strings connected to a bit line. The bit line extends in a first direction. The semiconductor device additionally includes a first cell row disposed in the peripheral circuit region and including a plurality of first cells arranged in a second direction crossing the first direction. The first and second directions being parallel to an upper surface of the substrate. The semiconductor device further includes a plurality of first interconnect lines each having a longitudinal axis in the first direction and connected to the plurality of first cells, and a plurality of first power lines extending in the second direction and connected to the plurality of first cells through the first interconnect lines.

Abstract: An electronic design automation method configured to automatically design a semiconductor device includes generating a site-row having a unit height based on a standard cell having the unit height, and generating metal routing tracks which begin at an offset point spaced a specific distance from an origin point of the site-row. The unit height is a non-integer multiple of a spacing of metal lines of one of interconnection layers of the semiconductor device. Using this process, a layout of a plurality of standard cells on a plurality of site-rows, and constituting a Floorplan of the semiconductor device, is generated.

Abstract: A semiconductor device includes a substrate including a cell array region and a peripheral circuit region. The semiconductor device further includes a cell array disposed in the cell array region and including a plurality of cell strings connected to a bit line. The bit line extends in a first direction. The semiconductor device additionally includes a first cell row disposed in the peripheral circuit region and including a plurality of first cells arranged in a second direction crossing the first direction. The first and second directions being parallel to an upper surface of the substrate. The semiconductor device further includes a plurality of first interconnect lines each having a longitudinal axis in the first direction and connected to the plurality of first cells, and a plurality of first power lines extending in the second direction and connected to the plurality of first cells through the first interconnect lines.

Abstract: An electronic design automation method configured to automatically design a semiconductor device includes generating a site-row having a unit height based on a standard cell having the unit height, and generating metal routing tracks which begin at an offset point spaced a specific distance from an origin point of the site-row. The unit height is a non-integer multiple of a spacing of metal lines of one of interconnection layers of the semiconductor device. Using this process, a layout of a plurality of standard cells on a plurality of site-rows, and constituting a Floorplan of the semiconductor device, is generated.