Abstract: The display device includes a first base portion; a semiconductor layer disposed on the first base portion and including a source region, a drain region and a channel region; a first insulating layer disposed on the semiconductor layer; a gate line disposed on the first insulating layer extending in a first direction and overlapping the channel region; a second insulating layer disposed on the gate line; a first connection plug formed in the first and second insulating layer filling a first connection hole exposing the source region; a second connection plug formed in the first and second insulating layer filling a second connection hole exposing the drain region; a first and second conductive pattern disposed on the second insulating layer; a pixel electrode disposed on the second insulating layer and electrically connected to the first conductive pattern; and a data line disposed on the second insulating layer to extend in a second direction.

Abstract: A display substrate includes a base substrate including a display area in which signal lines and pixels are arranged and a peripheral area surrounding the display area, pads disposed in the peripheral area and receiving an electrical signal, fan-out lines connecting the pads and the signal lines, and static electricity breakup circuits comprising a breakup line that crosses the fan-out lines, and static electricity prevention circuits respectively connected to the fan-out lines. Parts of the static electricity prevention circuits are connected to adjacent fan-out lines and are commonly connected to the one of the breakup lines through a common contact part.

Abstract: A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node.

Abstract: A display device includes pixels arranged in a matrix form, gate lines extending in a first direction; data lines extending in a second direction, first and second unit pixel columns, each defined by adjacent data lines and the pixels connected thereto, first and second channels which transmit data signals to each of the first and second unit pixel columns, and a line selector which connects the first and second channels to the data lines and provides data voltages to the data lines in response to control signals, where a pixel connected to a first gate line is connected to a data line at a side thereof, a pixel connected to a second gate line is connected to a data line at the other side thereof, and each of the first and second channels is connected to a data line of each of the first and second unit pixel columns.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.

Abstract: A display apparatus includes a plurality of pixels. A pixel includes a first capacitor connected between a first voltage line receiving a first driving signal and a first node, a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal and a second electrode connected to a second node, an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal, a second capacitor connected between an m-th data line and the second node (wherein, ‘m’ is a natural number) and a second transistor comprising a control electrode connected to an n-th scan line (wherein, ‘n’ is a natural number), a first electrode connected to the first node and a second electrode connected to the second node.

Abstract: A coupling compensator for a display panel and a display device including the coupling compensator are disclosed. In one aspect, the coupling compensator includes a memory configured to receive grayscale data and store the grayscale data and a first data converter configured to convert the grayscale data to a plurality of grayscale data voltages including first and second grayscale data voltages. The compensator also includes a coupling voltage calculator configured to calculate a line coupling voltage generated on a data line based on the difference between the first grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an (N?1)th row and the second grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an Nth row, where the N is an integer equal to or greater than 2.

Abstract: An event signal processing method and apparatus are provided. The event signal processing method includes receiving, from an event-based sensor, event signals including timestamps, generating a first timestamp map based on the timestamps, and interpolating a new timestamp into the first timestamp map based on at least two timestamps of the first timestamp map, to generate a second timestamp map.

Abstract: An apparatus and method for recognizing a speech, and an apparatus and method for generating a noise-speech recognition model are provided. The speech recognition apparatus includes a location determiner configured to determine a location of the apparatus, a noise model generator configured to generate a noise model corresponding to the location by collecting noise data related to the location, and a noise model transmitter configured to transmit the noise model to a server.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: Provided is an apparatus and corresponding method to control sound. The apparatus includes a genre determiner configured to determine a genre of sound data by using a genre recognition model, an equalizer setter configured to set an equalizer according to the determined genre, and a reproducer configured to reproduce the sound data based on the set equalizer.

Abstract: An array substrate for a touch sensor in-cell type display device is disclosed. The array includes a base substrate, a plurality of pixels disposed on the base substrate and including a plurality of pixel rows and a plurality of pixel columns, a gate line extending in a first direction on the base substrate and disposed above and below in each pixel row, a data line extending in a second direction intersecting with the first direction on the base substrate and disposed in every two pixel columns, a touch sensing line extending in the second direction on the base substrate and parallel to the data line, a plurality of touch blocks provided by grouping the plurality of pixels by a predetermined number on the base substrate, and a common electrode disposed in each of the plurality of touch blocks.

Abstract: A display device includes: a first substrate including a touch region for sensing a touch and a peripheral area surrounding the touch region; a second substrate facing the first substrate; thin film transistors positioned on the first substrate; pixel electrodes connected to the thin film transistors; common electrodes arranged to transmit a common voltage; sensing wires connected to the common electrodes and arranged to transmit a detection signal for sensing a touch; and a transparent electrode layer positioned on a first surface of the second substrate, the transparent electrode layer having a portion overlapping the peripheral area, and having at least one opening positioned over the touch region.

Abstract: There is provided a display device including a display including a first pixel connected to a first data line and a second pixel connected to a second data line, a data signal generator configured to generate an output signal, and a signal divider configured to divide the output signal, to generate a first data signal and a second data signal, and to apply the first data signal and the second data signal to the first data line and the second data line, respectively, wherein the data signal generator is configured to generate the output signal based on a coupling effect of a first parasitic capacitor formed between the first data line and the second data line and a coupling effect of a parasitic capacitor of a data line formed by the first data line and second data line.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.

Abstract: A gate driver includes a plurality of stage circuits to output a clock signal from the outside as gate signals. A jth stage circuit includes an input unit to charge a first node at an initial voltage when a first input signal is input to a first input terminal, a buffer unit to output the clock signal as a gate signal to an output terminal when the initial voltage is supplied to the first node, a holding unit to maintain the first node at a reset power source level when the clock signal is supplied to the holding unit, and an inverter unit to supply the clock signal or the reset power source to the holding unit. The input unit maintains the first node at a second input signal input voltage to a second input terminal when a third input signal is input to a third input terminal.

Abstract: Embodiments relate to a display device including: a first base substrate; gate lines disposed on the first base substrate, the gate lines extending in a first direction; parasitic capacitance electrodes coupled to the gate lines; data lines extending in a second direction crossing the first direction; transistors, each coupled to one of the gate lines and coupled to one of the data lines; and pixels sequentially arranged in the first direction, each of the pixels coupled to a corresponding one of the transistors, respectively. Each of the transistors includes a gate electrode, a source electrode, and a drain electrode, and at least two drain electrodes among the drain electrodes of the transistors each overlap a corresponding one of the parasitic capacitance electrodes in different areas as viewed from a plan view.

Abstract: There is provided a shift register including a plurality of stages sequentially coupled to an input terminal configured to receive a start pulse, wherein each of the plurality of stages includes a first transistor coupled between a first clock input terminal and an output terminal and having a first gate electrode coupled to a first node, a second transistor coupled between the output terminal and a power input terminal and having a second gate electrode coupled to a second clock input terminal, and a third transistor coupled between the first node and a first input terminal configured to receive the start pulse or an output signal of a previous stage of the stages, the third transistor having a third gate electrode coupled to the second clock input terminal.