Patents by Inventor Young-way Teh

Young-way Teh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040065956
    Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.
    Type: Application
    Filed: October 6, 2003
    Publication date: April 8, 2004
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Young-Way Teh, Victor Seng Keong Lim, Ting Cheong Ang
  • Patent number: 6649517
    Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: November 18, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Young-Way Teh, Victor Seng Keong Lim, Ting Cheong Ang
  • Publication number: 20020175414
    Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.
    Type: Application
    Filed: May 18, 2001
    Publication date: November 28, 2002
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Young-Way Teh, Victor Seng Keong Lim, Ting Cheong Ang
  • Patent number: 6406975
    Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: June 18, 2002
    Assignee: Chartered Semiconductor Manufacturing Inc.
    Inventors: Victor Seng Keong Lim, Young-Way Teh, Ting-Cheong Ang, Alex See, Yong Kong Siew
  • Patent number: 6380106
    Abstract: A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: April 30, 2002
    Assignee: Chartered Semiconductor Manufacturing Inc.
    Inventors: Seng Keong Victor Lim, Young-way Teh, Ting-Cheong Ang, Alex See, Yong Kong Siew