Abstract: An exemplary embodiment provides an intruder detection method capable of accurately detecting an intruder and estimating an abnormal behavior of the intruder even when viewpoints of acquired images are different from each other. An intruder detection method is suitable for being performed by an intruder detection device for detecting an intruder based on images and includes: receiving input images acquired by multiple cameras; extracting feature maps associated with a plurality of viewpoints by applying the input images to a plurality of convolutional neural networks provided separately for the plurality of viewpoints of the images; and detecting the intruder based on the feature maps associated with the plurality of viewpoints.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are ref lowed and fused together.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: A semiconductor package and method for producing the same has a substrate. A prepackaged semiconductor device is coupled to the substrate. At least one die is coupled to a top surface of the prepackaged semiconductor device. An adhesive layer is laid between the prepackaged semiconductor device and the first die to coupled the two together. A mold compound is then used to encapsulate the semiconductor package.

Abstract: A semiconductor stacking structure and method of producing the same has a flexible substrate. A plurality of apertures is formed on the flexible substrate. The plurality of apertures may be formed in groups for coupling semiconductor devices to the flexible substrate. A plurality of traces is formed on the flexible substrate for coupling the plurality of apertures together. A first semiconductor device is coupled to a first side of the flexible substrate. A first adhesive layer is placed on a first side of the flexible substrate for coupling the first semiconductor device to the first side of the flexible substrate. A plurality of contacts is coupled to a second side of the flexible substrate. The contacts and the first adhesive layer liquefy and flow into designated apertures when heated to couple the contacts to the first semiconductor device.

Abstract: Embodiments of semiconductor packages containing a stack of at least two semiconductor chips are disclosed, along with methods of making the same. One embodiment includes a substrate, which may be a ball grid array substrate or a metal leadframe. The stack of semiconductor chips is mounted to the substrate. Each semiconductor chip has a plurality of bond pads on an active surface thereof. The bond pads of the first semiconductor chip face corresponding ones of the bond pads of the second semiconductor chip, and are joined thereto through an electrically conductive joint. One of a plurality of bond wires extend from each of the joints to the substrate. Accordingly, pairs of bond pads of the first and second semiconductor chips are electrically interconnected, and are electrically connected to the substrate through the respective bond wire.

Abstract: A method of fabricating a semiconductor package is provided, which realizes a small-size semiconductor package without performance deterioration, to meet a tendency to miniaturization of electronic products in which semiconductor packages are mounted, such as communication apparatus and computer, provides a new type of compact multi-pin semiconductor package as large as a semiconductor chip mounted thereon, and accomplishes a semiconductor package having multi-function to minimize its mounting area on an electronic product, resulting in minimizing of the products.

Abstract: A method of fabricating a semiconductor package is provided, which realizes a small-size semiconductor package without performance deterioration, to meet a tendency to miniaturization of electronic products in which semiconductor packages are mounted, such as communication apparatus and computer, provides a new type of compact multi-pin semiconductor package as large as a semiconductor chip mounted thereon, and accomplishes a semiconductor package having multi-function to minimize its mounting area on an electronic product, resulting in minimizing of the products.

Abstract: A bump chip scale semiconductor package. In the bump chip scale semiconductor package, the chip bumps are directly formed on the chip pads of a semiconductor chip. The above chip bumps are used as the signal input and output terminals of the package and are used as surface mounting joints when the chip is mounted to a mother board.

Abstract: A method for marking poor quality printed circuit board units of a printed circuit board strip for ball grid array semiconductor packages wherein at least one degradation-indicating hole is at least partially formed in a poor quality printed circuit board unit of the strip at a region defined between an outer edge of the resin seal molding region of the unit and a cutting line formed on the printed circuit board strip to separate the unit from the strip. Even when a plurality of printed circuit board strips are packed in a vacuum under the condition in which they are stacked, there is no phenomenon that those strips in the pack are permanently deformed, for example, permanently bent. Also, there is no phenomenon that melt resin is leaked from the mold, thereby causing it to be bled out onto the upper surface of the printed circuit board strip. Since no paint is used to mark poor quality printed circuit board units, there is no problem associated with the use of the paint such as a contamination.

Abstract: A printed circuit board for a BGA semiconductor package provided at one corner thereof with a degating opening serving as a mold runner gate during a process of molding a resin seal adapted to protect the semiconductor chip and serving as a region for degating a surplus resin formed after the molding process and a method for molding a BGA semiconductor using the printed circuit board. The degating opening has an inverted triangular shape having curved lateral sides and a vertex, at which the lateral sides join together, disposed in a region for forming the resin seal, or an inverted trapezoidal shape having one end disposed in the resin seal region.

Abstract: A chip size semiconductor package with a light, thin, simple and compact structure having a reduced size of its semiconductor chip while having an increased number of pins and without degrading its functions. For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.

Abstract: A ball grid array semiconductor package using a flexible circuit board, in which the flexible circuit board has no conductive via hole nor solder mask while having a thin structure formed at only one surface thereof with a circuit pattern having a small length. The flexible circuit board is mounted with a metallic carrier frame to achieve an easy handling thereof, a reduction in the inductance, impedance and coupling effect of adjacent circuit patterns and an easy discharge of heat from a semiconductor chip, thereby achieving an improvement in electrical performance and an improvement in heat discharge performance. The metallic carrier frame has a plurality of openings adapted to increase the bonding force between an encapsulate and constituting elements of the package, thereby removing a bending phenomenon of the package, and a method for fabricating such a BGA semiconductor package. The invention also provides a method for fabricating such a BGA semiconductor package.

Abstract: A semiconductor chip scale package and method of producing the package are disclosed. The package has a semiconductor chip having signal leading bumps. A PCB is electrically connected to the chip, thus transmitting input and output signals. A plurality of solder balls are formed on the lower surface of the PCB and are used as signal input and output terminals. An epoxy resin layer bonds the chip to the PCB. The PCB consists of a polymer resin substrate, a copper circuit pattern and a solder mask. The copper circuit pattern has a chip bump land and a solder ball land. The lands electrically connect the signal leading bumps to the solder balls. The package has a package size being similar to or slightly larger than a semiconductor chip within 120 % of the size of the chip.

Abstract: A method of forming chip bumps of a bump chip scale semiconductor package, such a package and a chip bump are disclosed. In the bump chip scale semiconductor package produced by the above method, the chip bumps are directly formed on the chip pads of a semiconductor chip. The above chip bumps are used as the signal input and output terminals of the package and are used as surface mounting joints when the chip is mounted to a mother board.

Abstract: A ball grid array semiconductor package includes a semiconductor chip mounted to the top side of a printed circuit board (PCB), having a copper circuit pattern at a position outside a chip mounting zone. A plurality of bond wires electrically connect the chip to the copper circuit pattern. A rectangular ring-shaped metal heat spreader is attached to the PCB surrounding the chip, with the outer periphery of the ring substantially coextensive with the outer periphery of the PCB. A molding compound is provided in a zone inside the heat spreader thus protecting the chip and wires from atmosphere, while the molding compound extends to a heat spreader portion, leaving other portions of the heat spreader exposed to atmosphere. A plurality of solder balls are included on the bottom side of the PCB and are used as signal input and output terminals of the package. The BGA package easily dissipates heat during the operation of the package, improving the operational reliability of the package.