Patents by Inventor Youngok Pino

Youngok Pino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis
    Patent number: 10153769
    Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: December 11, 2018
    Assignee: New York University
    Inventors: Ozgur Sinanoglu, Youngok Pino, Jeyavijayan Rajendran, Ramesh Karri
  • System, method and computer-accessible medium for facilitating logic encryption
    Patent number: 9817980
    Abstract: Exemplary systems, methods and computer-accessible mediums for encrypting at least one integrated circuit (IC) can include determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC, and inserting the gate(s) into the IC(s) at the location(s). The interference graph can be constructed based at least in part on an effect of the location(s) on at least one further location of the IC(s).
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 14, 2017
    Assignee: New York University
    Inventors: Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, Ramesh Karri
  • SYSTEMS, PROCESSES AND COMPUTER-ACCESSIBLE MEDIUM FOR PROVIDING LOGIC ENCRYPTION UTILIZING FAULT ANALYSIS
    Publication number: 20160049935
    Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.
    Type: Application
    Filed: July 13, 2015
    Publication date: February 18, 2016
    Inventors: OZGUR SINANOGLU, YOUNGOK PINO, JEYAVIJAYAN RAJENDRAN, RAMESH KARRI
  • SYSTEM, METHOD AND COMPUTER-ACCESSIBLE MEDIUM FOR FACILITATING LOGIC ENCRYPTION
    Publication number: 20160034694
    Abstract: Exemplary systems, methods and computer-accessible mediums for encrypting at least one integrated circuit (IC) can include determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC, and inserting the gate(s) into the IC(s) at the location(s). The interference graph can be constructed based at least in part on an effect of the location(s) on at least one further location of the IC(s).
    Type: Application
    Filed: March 14, 2014
    Publication date: February 4, 2016
    Inventors: JEYAVIJAYAN RAJENDRAN, YOUNGOK PINO, OZGUR SINANOGLU, RAMESH KARRI
  • Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis
    Patent number: 9081929
    Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: July 14, 2015
    Assignee: New York University
    Inventors: Ozgur Sinanoglu, Youngok Pino, Jeyavijayan Rajendran, Ramesh Karri