Abstract: An electronic device includes a cache memory including a memory space for storing a first cache set including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits representing whether corresponding sector data of the plurality of sector data are modified, a memory controller, connected to a plurality of data lines and a data mask line, for receiving the plurality of sector data and the plurality of dirty bits from the cache memory, setting a logic level of a data mask signal based on a logic level of each of the plurality of dirty bits, and outputting the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line, and a memory device, connected to the plurality of data lines and the data mask line, for receiving the plurality of sector data through the plurality of data lines, and receiving the data mask signal through the data mask line.

Abstract: A semiconductor memory device includes: a memory core including memory cells and configured to output core data stored in the memory cells in response to a read request, a command decoder configured to decode at least one command input from an external device, a command log register configured to sequentially store the at least one command in response to a register enable signal and output the at least one command as a command log in response to a command log read signal, and a mode register set configured to generate the register enable signal or the command log read signal in response to a mode register set command transmitted to the command decoder.

Abstract: An interconnect module device is provided. The interconnect module device includes a line control command (LCC) detecting circuit configured to identify an LCC signal; an equalizer control circuit configured to generate a control signal based on the LCC signal; a receiving equalizer configured to perform receiving equalization on a first signal received from a first universal flash storage (UFS) device based on the control signal to generate a second signal; and a transmitting equalizer configured to perform transmitting equalization on the second signal to generate a third signal based on the control signal, and transmit the third signal to a second UFS device.

Abstract: An interconnect module device is provided. The interconnect module device includes a line control command (LCC) detecting circuit configured to identify an LCC signal; an equalizer control circuit configured to generate a control signal based on the LCC signal; a receiving equalizer configured to perform receiving equalization on a first signal received from a first universal flash storage (UFS) device based on the control signal to generate a second signal; and a transmitting equalizer configured to perform transmitting equalization on the second signal to generate a third signal based on the control signal, and transmit the third signal to a second UFS device.

Abstract: A universal flash storage (UFS) device includes a UFS data lane comprising a first UFS lane for a first direction in which data is output to a UFS host, a second UFS lane for a second direction in which data is received from the UFS host, and bidirectional UFS lanes capable of switching the first direction and the second direction according to an operation mode. A UFS device controller switches a data transmission direction of the bidirectional UFS lanes, based on a control signal indicating the operation mode.

Abstract: An electronic device includes a cache memory including a memory space for storing a first cache set including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits representing whether corresponding sector data of the plurality of sector data are modified, a memory controller, connected to a plurality of data lines and a data mask line, for receiving the plurality of sector data and the plurality of dirty bits from the cache memory, setting a logic level of a data mask signal based on a logic level of each of the plurality of dirty bits, and outputting the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line, and a memory device, connected to the plurality of data lines and the data mask line, for receiving the plurality of sector data through the plurality of data lines, and receiving the data mask signal through the data mask line.