Patents by Inventor Young-Seop Rah
Young-Seop Rah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9202932Abstract: In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.Type: GrantFiled: March 15, 2013Date of Patent: December 1, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Woo Paek, Jung-Dal Choi, Young-Seop Rah, Byung-Kwan You, Seok-Won Lee
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Publication number: 20130256781Abstract: In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.Type: ApplicationFiled: March 15, 2013Publication date: October 3, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Seung-Woo PAEK, Jung-Dal Choi, Young-Seop Rah, Byung-Kwan You, Seok-Won Lee
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Patent number: 8486802Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.Type: GrantFiled: September 20, 2011Date of Patent: July 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-hoon Jang, Young-bae Yoon, Hee-soo Kang, Young-seop Rah, Jeong-dong Choe
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Patent number: 8368182Abstract: Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern.Type: GrantFiled: October 5, 2009Date of Patent: February 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Young-ho Lee, Jae-hwang Sim, Young-seop Rah
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Patent number: 8343812Abstract: On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.Type: GrantFiled: August 5, 2011Date of Patent: January 1, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Sung Song, Soon-Moon Jung, Han-Soo Kim, Young-Seop Rah, Won-Seok Cho, Yang-Soo Son, Jong-Hyuk Kim, Young-Chul Jang
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Publication number: 20120009759Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.Type: ApplicationFiled: September 20, 2011Publication date: January 12, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-hoon JANG, Young-bae Yoon, Hee-soo Kang, Young-seop Rah, Jeong-dong Choe
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Publication number: 20110287590Abstract: On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.Type: ApplicationFiled: August 5, 2011Publication date: November 24, 2011Inventors: Min-Sung Song, Soon-Moon Jung, Han-Soo Kim, Young-Seop Rah, Won-Seok Cho, Yang-Soo Son, Jong-Hyuk KIm, Young-Chul Jang
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Patent number: 8048727Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.Type: GrantFiled: January 14, 2010Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Jang, Soon-Moon Jung, Young-Seop Rah, Han-Byung Park
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Patent number: 8035152Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.Type: GrantFiled: June 22, 2009Date of Patent: October 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-hoon Jang, Young-bae Yoon, Hee-soo Kang, Young-seop Rah, Jeong-dong Choe
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Publication number: 20100155906Abstract: Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern.Type: ApplicationFiled: October 5, 2009Publication date: June 24, 2010Inventors: Young-ho Lee, Jae-hwang Sim, Young-seop Rah
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Publication number: 20100120217Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.Type: ApplicationFiled: January 14, 2010Publication date: May 13, 2010Inventors: Jae-Hoon Jang, Soon-Moon Jung, Young-Seop Rah, Han-Byung Park
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Patent number: 7671389Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.Type: GrantFiled: March 21, 2006Date of Patent: March 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Jang, Soon-Moon Jung, Young-Seop Rah, Han-Byung Park
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Publication number: 20100012980Abstract: On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.Type: ApplicationFiled: July 17, 2009Publication date: January 21, 2010Inventors: Min-Sung Song, Soon-Moon Jung, Han-Soo Kim, Young-Seop Rah, Won-Seok Cho, Yang-Soo Son, Jong-Hyuk Kim, Young-Chul Jang
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Patent number: 7646664Abstract: A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.Type: GrantFiled: October 9, 2007Date of Patent: January 12, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hoo-Sung Cho, Soon-Moon Jung, Young-Seop Rah, Jae-Hoon Jang, Jae-Hun Jeong, Jun-Beom Park
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Publication number: 20100001366Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.Type: ApplicationFiled: June 22, 2009Publication date: January 7, 2010Inventors: Dong-hoon Jang, Young-bae Yoon, Hee-soo Kang, Young-seop Rah, Jeong-dong Choe
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Patent number: 7602028Abstract: A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.Type: GrantFiled: January 17, 2007Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yang-Soo Son, Young-Seop Rah, Won-Seok Cho, Soon-Moon Jung, Jae-Hoon Jang, Young-Chul Jang
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Patent number: 7589375Abstract: A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.Type: GrantFiled: December 20, 2006Date of Patent: September 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Jang, Soon-Moon Jung, Jong-Hyuk Kim, Young-Seop Rah, Han-Byung Park
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Publication number: 20080087932Abstract: A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.Type: ApplicationFiled: January 17, 2007Publication date: April 17, 2008Inventors: Yang-Soo Son, Young-Seop Rah, Won-Seok Cho, Soon-Moon Jung, Jae-Hoon Jang, Young-Chul Jang
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Publication number: 20080084729Abstract: A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.Type: ApplicationFiled: October 9, 2007Publication date: April 10, 2008Inventors: Hoo-Sung Cho, Soon-Moon Jung, Young-Seop Rah, Jae-Hoon Jang, Jae-Hun Jeong, Jun-Beom Park
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Publication number: 20070096197Abstract: A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.Type: ApplicationFiled: December 20, 2006Publication date: May 3, 2007Inventors: Jae-Hoon Jang, Soon-Moon Jung, Jong-Hyuk Kim, Young-Seop Rah, Han-Byung Park