Abstract: A display device includes a driving voltage line and a plurality of data lines extending in a first direction, a first driving transistor electrically connected to the driving voltage line, a first switching transistor electrically connected to the first driving transistor and including a first switching semiconductor layer extending in a second direction crossing the first direction and a first switching gate electrode overlapping a channel region of the first switching semiconductor layer, and a first storage capacitor electrically connected to the first driving transistor and the first switching transistor, where the first switching semiconductor layer is electrically connected to a first data line, the first switching semiconductor layer crosses a second data line between the channel region and the first data line, and a crossing region of an edge of the first switching semiconductor layer and an edge of the second data line overlaps a first protection layer.

Abstract: Disclosed is an electroluminescent display device comprising an active area for displaying an image, a dummy area provided in the periphery of the active area, wherein an image is not displayed in the dummy area, a scan line, an initializing line and an emission line arranged along a first direction in the dummy area, a high power source line and a data line arranged along a second direction, which intersects with the first direction, in the dummy area, and a plurality of thin film transistors disposed in the dummy area, wherein the plurality of thin film transistors include a driving thin film transistor, a switching thin film transistor provided to connect the driving thin film transistor and the data line with each other, and an operation control thin film transistor provided to connect the driving thin film transistor and the high power source line with each other, wherein the switching thin film transistor and the operation control thin film transistor are disconnected from each other.

Abstract: A display device includes a driving voltage line and a plurality of data lines extending in a first direction, a first driving transistor electrically connected to the driving voltage line, a first switching transistor electrically connected to the first driving transistor and including a first switching semiconductor layer extending in a second direction crossing the first direction and a first switching gate electrode overlapping a channel region of the first switching semiconductor layer, and a first storage capacitor electrically connected to the first driving transistor and the first switching transistor, where the first switching semiconductor layer is electrically connected to a first data line, the first switching semiconductor layer crosses a second data line between the channel region and the first data line, and a crossing region of an edge of the first switching semiconductor layer and an edge of the second data line overlaps a first protection layer.

Abstract: A display device includes a driving voltage line and a plurality of data lines extending in a first direction, a first driving transistor electrically connected to the driving voltage line, a first switching transistor electrically connected to the first driving transistor and including a first switching semiconductor layer extending in a second direction crossing the first direction and a first switching gate electrode overlapping a channel region of the first switching semiconductor layer, and a first storage capacitor electrically connected to the first driving transistor and the first switching transistor, where the first switching semiconductor layer is electrically connected to a first data line, the first switching semiconductor layer crosses a second data line between the channel region and the first data line, and a crossing region of an edge of the first switching semiconductor layer and an edge of the second data line overlaps a first protection layer.

Abstract: A display device includes a driving voltage line and a plurality of data lines extending in a first direction, a first driving transistor electrically connected to the driving voltage line, a first switching transistor electrically connected to the first driving transistor and including a first switching semiconductor layer extending in a second direction crossing the first direction and a first switching gate electrode overlapping a channel region of the first switching semiconductor layer, and a first storage capacitor electrically connected to the first driving transistor and the first switching transistor, where the first switching semiconductor layer is electrically connected to a first data line, the first switching semiconductor layer crosses a second data line between the channel region and the first data line, and a crossing region of an edge of the first switching semiconductor layer and an edge of the second data line overlaps a first protection layer.

Abstract: Disclosed is an electroluminescent display device comprising an active area for displaying an image, a dummy area provided in the periphery of the active area, wherein an image is not displayed in the dummy area, a scan line, an initializing line and an emission line arranged along a first direction in the dummy area, a high power source line and a data line arranged along a second direction, which intersects with the first direction, in the dummy area, and a plurality of thin film transistors disposed in the dummy area, wherein the plurality of thin film transistors include a driving thin film transistor, a switching thin film transistor provided to connect the driving thin film transistor and the data line with each other, and an operation control thin film transistor provided to connect the driving thin film transistor and the high power source line with each other, wherein the switching thin film transistor and the operation control thin film transistor are disconnected from each other.

Abstract: An electroluminescent display and a method of driving the same are disclosed. The electroluminescent display includes a display panel including a plurality of pixels electrically connected to a plurality of data lines and a plurality of gate lines. Each pixel includes a driving element adjusting a current of a light emitting element depending on a gate-to-source voltage, and a switching element supplying a second voltage to the driving element in response to a gate-on voltage of an emission control signal. The switching element is turned off in response to a gate-off voltage of the emission control signal during a real-time compensation time. A source voltage of the driving element is changed during the real-time compensation time.

Abstract: An electroluminescence display device according to an embodiment includes a plurality of sub-pixels. Each of the plurality of sub-pixels includes a Node-A electrically connected to an electrode of a storage capacitor and a gate electrode of a P-type driving transistor, an N-type switching transistor configured to switch an electrical connection between a Node-B electrically connected to a data line and the Node-A, a Node-C configured to supply ELVDD voltage and electrically connected to another electrode of the storage capacitor and a first electrode of the P-type driving transistor, a Node-D configured to supply current to an electroluminescence diode and electrically connected to a second electrode of the P-type driving transistor, and a first transistor configured to switch an electrical connection between the Node-A and the Node-D.

Abstract: A gate driver circuit, a display device, and a method of driving the display device are disclosed. The gate driver circuit includes a first transistor supplying a start signal to a Q node in response to a clock, a second transistor adjusting a gate voltage of the first transistor in response to the clock, a third transistor adjusting a gate voltage of the second transistor in response to the start signal, a fourth transistor changing a voltage of a QB node, a fifth transistor switching a current path between the first transistor and the Q node in response to a first line control signal, a sixth transistor supplying a gate-off voltage to an output node, a seventh transistor supplying a gate-on voltage to the output node, and an eighth transistor supplying a second line control signal to the QB node.

Abstract: A gate driver circuit and a display device using the same are disclosed. The gate driver circuit includes a first transistor supplying a start signal to a Q node in response to a clock, a second transistor adjusting a gate voltage of the first transistor in response to the clock, a third transistor adjusting a gate voltage of the second transistor in response to the start signal, a fourth transistor changing a voltage of a QB node, a fifth transistor switching a current path between the first transistor and the Q node in response to a first line control signal, a sixth transistor supplying a gate-off voltage to an output node, a seventh transistor supplying a gate-on voltage to the output node, and an eighth transistor supplying a second line control signal to the QB node.

Abstract: A gate driver circuit and a display device using the same are disclosed. The gate driver circuit includes a first transistor supplying a start signal to a Q node in response to a clock, a second transistor adjusting a gate voltage of the first transistor in response to the clock, a third transistor adjusting a gate voltage of the second transistor in response to the start signal, a fourth transistor changing a voltage of a QB node, a fifth transistor switching a current path between the first transistor and the Q node in response to a first line control signal, a sixth transistor supplying a gate-off voltage to an output node, a seventh transistor supplying a gate-on voltage to the output node, and an eighth transistor supplying a second line control signal to the QB node.

Abstract: A gate driver circuit, a display device, and a method of driving the display device are disclosed. The gate driver circuit includes a first transistor supplying a start signal to a Q node in response to a clock, a second transistor adjusting a gate voltage of the first transistor in response to the clock, a third transistor adjusting a gate voltage of the second transistor in response to the start signal, a fourth transistor changing a voltage of a QB node, a fifth transistor switching a current path between the first transistor and the Q node in response to a first line control signal, a sixth transistor supplying a gate-off voltage to an output node, a seventh transistor supplying a gate-on voltage to the output node, and an eighth transistor supplying a second line control signal to the QB node.

Abstract: An electroluminescent display and a method of driving the same are disclosed. The electroluminescent display includes a display panel including a plurality of pixels electrically connected to a plurality of data lines and a plurality of gate lines. Each pixel includes a driving element adjusting a current of a light emitting element depending on a gate-to-source voltage, and a switching element supplying a second voltage to the driving element in response to a gate-on voltage of an emission control signal. The switching element is turned off in response to a gate-off voltage of the emission control signal during a real-time compensation time. A source voltage of the driving element is changed during the real-time compensation time.

Abstract: An electroluminescence display device according to an embodiment includes a plurality of sub-pixels. Each of the plurality of sub-pixels includes a Node-A electrically connected to an electrode of a storage capacitor and a gate electrode of a P-type driving transistor, an N-type switching transistor configured to switch an electrical connection between a Node-B electrically connected to a data line and the Node-A, a Node-C configured to supply ELVDD voltage and electrically connected to another electrode of the storage capacitor and a first electrode of the P-type driving transistor, a Node-D configured to supply current to an electroluminescence diode and electrically connected to a second electrode of the P-type driving transistor, and a first transistor configured to switch an electrical connection between the Node-A and the Node-D.