Abstract: An image signal processor includes a register and a disparity correction unit. The register stores disparity data obtained from a pattern image data that an image senor generates, and the image sensor includes a plurality of pixels, and each of the pixel includes at least a first photoelectric conversion element and a second photoelectric conversion element. The image sensor generates the pattern image data in response to a pattern image located at a first distance from the image sensor. The disparity correction unit corrects a disparity distortion of an image data based on the disparity data to generate a result image data, and the image senor generates the image data by capturing an object.

Abstract: Provided is a community management method including: receiving, from a first terminal, a generation request for a standby community; generating the standby community including a user of the first terminal as a participant, according to the generation request for the standby community; and generating a regular community including participants of the standby community as members in response to a number of the participants of the standby community reaching a target number of the standby community, wherein a writing function is restricted in the standby community and allowed in the regular community.

Abstract: The non-volatile memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: The memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: The non-volatile memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.

Abstract: A dynamic power control system includes an external power input terminal receiving a first output electric current from a power management circuit outside of the memory device; a variable charge pump receiving a second input voltage and a second input electric current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and a second output electric current to the memory device; and a feedback controller to compare a ratio of the first output electric current to the first input electric current and a ratio of the second output electric current to the second input electric current, and to select one of the power management circuit and the variable charge pump to supply power to the memory device, according to the comparison result.

Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes an external power supply voltage terminal configured to receive an external power supply voltage, an external ground voltage terminal configured to receive an external ground voltage, a ground voltage noise detector configured to detect a difference between the external ground voltage and an internal ground voltage of an internal ground voltage node and generate a ground voltage noise reference voltage, an internal power supply voltage reference voltage generator configured to generate an internal power supply voltage reference voltage based on the external power supply voltage and the ground voltage noise reference voltage, and an internal power supply voltage driver configured to generate an internal power supply voltage based on the internal power supply voltage reference voltage.

Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes an external power supply voltage terminal configured to receive an external power supply voltage, an external ground voltage terminal configured to receive an external ground voltage, a ground voltage noise detector configured to detect a difference between the external ground voltage and an internal ground voltage of an internal ground voltage node and generate a ground voltage noise reference voltage, an internal power supply voltage reference voltage generator configured to generate an internal power supply voltage reference voltage based on the external power supply voltage and the ground voltage noise reference voltage, and an internal power supply voltage driver configured to generate an internal power supply voltage based on the internal power supply voltage reference voltage.

Abstract: A high voltage switch circuit includes a first transistor, a first depletion mode transistor, a level shifter, a control signal generator, a second transistor and a second depletion mode transistor. The first transistor transmits the second driving voltage to an output terminal in response to a first gate signal. The first depletion mode transistor transmits the second driving voltage to the first transistor in response to feedback from the output terminal. The control signal generator generates first and second control signals in response to a level-shifted enable signal. The second transistor has a gate electrode connected to the first voltage and is turned on and off in response to the second control signal at a first end of the second transistor. The second depletion mode transistor is connected between a second end of the second transistor and the output terminal, and has a gate electrode receiving the first control signal.

Abstract: A semiconductor package includes first through third memory chips. The first memory chip is arranged on a package substrate, the second memory chip is arranged on the first memory chip, and the third memory chip is arranged between the first memory chip and the second memory chip. Each of the first through third memory chips includes a memory cell array storing data, stress detectors, a stress index generator, and a control circuit. The stress detectors are formed and distributed in a substrate, and detect stacking stress in response to an external voltage to output a plurality of sensing currents. The stress index generator converts the plurality of sensing currents into stress index codes. The control circuit adjusts a value of a feature parameter associated with an operating voltage of a corresponding memory chip, based on at least a portion of the stress index codes.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: A dynamic power control system includes an external power input terminal receiving a first output electric current from a power management circuit outside of the memory device; a variable charge pump receiving a second input voltage and a second input electric current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and a second output electric current to the memory device; and a feedback controller to compare a ratio of the first output electric current to the first input electric current and a ratio of the second output electric current to the second input electric current, and to select one of the power management circuit and the variable charge pump to supply power to the memory device, according to the comparison result.

Abstract: A high voltage switch circuit includes a first transistor, a first depletion mode transistor, a level shifter, a control signal generator, a second transistor and a second depletion mode transistor. The first transistor transmits the second driving voltage to an output terminal in response to a first gate signal. The first depletion mode transistor transmits the second driving voltage to the first transistor in response to feedback from the output terminal. The control signal generator generates first and second control signals in response to a level-shifted enable signal. The second transistor has a gate electrode connected to the first voltage and is turned on and off in response to the second control signal at a first end of the second transistor. The second depletion mode transistor is connected between a second end of the second transistor and the output terminal, and has a gate electrode receiving the first control signal.

Abstract: The memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.

Abstract: A semiconductor package includes first through third memory chips. The first memory chip is arranged on a package substrate, the second memory chip is arranged on the first memory chip, and the third memory chip is arranged between the first memory chip and the second memory chip. Each of the first through third memory chips includes a memory cell array storing data, stress detectors, a stress index generator, and a control circuit. The stress detectors are formed and distributed in a substrate, and detect stacking stress in response to an external voltage to output a plurality of sensing currents. The stress index generator converts the plurality of sensing currents into stress index codes. The control circuit adjusts a value of a feature parameter associated with an operating voltage of a corresponding memory chip, based on at least a portion of the stress index codes.

Abstract: A voltage generator includes a first trim unit and a second trim unit. The first trim unit generates a first voltage variable depending on temperature variation and a second voltage invariable irrespective of the temperature variation based on a power supply voltage, and performs a first trim operation by changing a level of the second voltage. The level of the second voltage at a first temperature becomes substantially the same as a level of the first voltage at the first temperature based on the first trim operation. The second trim unit generates an output voltage based on the power supply voltage, the first and second voltages, a reference voltage and a feedback voltage, and performs a second trim operation by adjusting variation of the output voltage depending on the temperature variation based on a result of the first trim operation.

Abstract: A voltage generator includes a first trim unit and a second trim unit. The first trim unit generates a first voltage variable depending on temperature variation and a second voltage invariable irrespective of the temperature variation based on a power supply voltage, and performs a first trim operation by changing a level of the second voltage. The level of the second voltage at a first temperature becomes substantially the same as a level of the first voltage at the first temperature based on the first trim operation. The second trim unit generates an output voltage based on the power supply voltage, the first and second voltages, a reference voltage and a feedback voltage, and performs a second trim operation by adjusting variation of the output voltage depending on the temperature variation based on a result of the first trim operation.