Abstract: The present disclosure relates to a chip on film package, in which communication wires for communication with a control circuit are disposed to traverse a semiconductor chip thereunder so as to simplify the wiring inside the semiconductor chip.

Abstract: The present disclosure relates to a chip on film package, in which communication wires for communication with a control circuit are disposed to traverse a semiconductor chip thereunder so as to simplify the wiring inside the semiconductor chip.

Abstract: Disclosed is a system for a display, which drives pixels using a double rate driving (DRD) method. The system includes a timing controller configured to provide a data packet and a lock signal, and a plurality of drivers each configured to restore display data and a clock of the data packet and output a source signal corresponding to the display data using the clock. The lock signal is fed back to the timing controller via the plurality of drivers. Each of the drivers outputs an internal lock signal, obtained by updating the lock signal with information on a restored clock, in next order. Each of the drivers may operate in a low power mode.

Abstract: Disclosed is a driving apparatus for a display, which drives pixels using a double rate driving (DRD) method. The driving apparatus includes a first latch circuit storing first pixel data, a second latch circuit storing second pixel data, a first selection circuit selecting one of the first pixel data and the second pixel data and outputting selection data, and a second selection circuit selecting one of the selection data of a pair of adjacent first selection units and outputting source data.

Abstract: Disclosed is a system for a display, which drives pixels using a double rate driving (DRD) method. The system includes a timing controller configured to provide a data packet and a lock signal, and a plurality of drivers each configured to restore display data and a clock of the data packet and output a source signal corresponding to the display data using the clock. The lock signal is fed back to the timing controller via the plurality of drivers. Each of the drivers outputs an internal lock signal, obtained by updating the lock signal with information on a restored clock, in next order. Each of the drivers may operate in a low power mode.

Abstract: Disclosed is a driving apparatus for a display, which drives pixels using a double rate driving (DRD) method. The driving apparatus includes a first latch circuit storing first pixel data, a second latch circuit storing second pixel data, a first selection circuit selecting one of the first pixel data and the second pixel data and outputting selection data, and a second selection circuit selecting one of the selection data of a pair of adjacent first selection units and outputting source data.

Abstract: The present disclosure discloses a display device that performs a read operation corresponding to a touch based on a multipoint interface (MPI) protocol. In the display device, a microcontroller and a plurality of drivers share MPI buses and perform the read operation for a touch, and turning on of reception buffers may be efficiently controlled by providing a wake-up signal by a selected driver designated by a read command of the microcontroller to unselected drivers at the time of completion of transmission of touch data.

Abstract: The present disclosure discloses a display device that performs a read operation corresponding to a touch based on a multipoint interface (MPI) protocol. In the display device, a microcontroller and a plurality of drivers share MPI buses and perform the read operation for a touch, and turning on of reception buffers may be efficiently controlled by providing a wake-up signal by a selected driver designated by a read command of the microcontroller to unselected drivers at the time of completion of transmission of touch data.

Abstract: A memory device that includes a memory cell array and control circuit in which the memory cell array includes a normal region including a first failed block and a redundant region including a first redundant block replacing the first failed block. The control circuit includes a mapping table storing replacement information. The control circuit refers to the mapping table for accessing the first redundant block. When testing the memory device, the control circuit writes “1” in the normal region and the first redundant block, writes “0” in the redundant region except the first redundant block, adds the replacement information regarding a second failed block and second redundant block in the redundant region to the mapping table and verifies the result of replacing the second failed block with the second redundant block based on entire data read from the memory cell array with respect to entire range assigned to the address signal.

Abstract: A memory device that includes a memory cell array and control circuit in which the memory cell array includes a normal region including a first failed block and a redundant region including a first redundant block replacing the first failed block. The control circuit includes a mapping table storing replacement information. The control circuit refers to the mapping table for accessing the first redundant block. When testing the memory device, the control circuit writes “1” in the normal region and the first redundant block, writes “0” in the redundant region except the first redundant block, adds the replacement information regarding a second failed block and second redundant block in the redundant region to the mapping table and verifies the result of replacing the second failed block with the second redundant block based on entire data read from the memory cell array with respect to entire range assigned to the address signal.

Abstract: A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

Abstract: A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

Abstract: A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

Abstract: A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

Abstract: Provided are a test pattern generating circuit which generates test patterns having various types and lengths and a semiconductor memory device which performs a test operation using the test pattern generating circuit. The test pattern generating circuit includes a plurality of register blocks which receive test signals input from an external tester through an input/output pad and load the test signals into the resister blocks in synchronization with a low-frequency clock signal; a register block control unit which controls the activation of the register blocks; and an output unit which is connected to the register blocks and outputs the signals loaded into the register blocks as test patterns in synchronization with a high-frequency clock signal.

Abstract: A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.

Abstract: An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by buffering the first data, sampling buffered first data responsive to a write data strobe (WDQS) signal, and parallelizing sampled data. The data pattern setting circuit sets a pattern of the second data responsive to a test mode signal and a data pattern select signal to generate third data. Accordingly, the semiconductor memory device including the input circuit may generate data of various patterns in a test mode, and may perform a high-speed test using a low-speed tester.

Abstract: Provided are a test pattern generating circuit which generates test patterns having various types and lengths and a semiconductor memory device which performs a test operation using the test pattern generating circuit. The test pattern generating circuit includes a plurality of register blocks which receive test signals input from an external tester through an input/output pad and load the test signals into the resister blocks in synchronization with a low-frequency clock signal; a register block control unit which controls the activation of the register blocks; and an output unit which is connected to the register blocks and outputs the signals loaded into the register blocks as test patterns in synchronization with a high-frequency clock signal.

Abstract: A memory device includes a plurality of test mode signal generating units and a plurality of test circuits. Each test mode signal generating unit generates a respective test mode signal for a respective test circuit. The test mode signal generating units generate the test mode signals in series for the test circuits. Each test mode signal generating unit may be disposed within a respective test circuit such that wiring is not necessary from the source of the test mode signals to the test circuits.

Abstract: An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by buffering the first data, sampling buffered first data responsive to a write data strobe (WDQS) signal, and parallelizing sampled data. The data pattern setting circuit sets a pattern of the second data responsive to a test mode signal and a data pattern select signal to generate third data. Accordingly, the semiconductor memory device including the input circuit may generate data of various patterns in a test mode, and may perform a high-speed test using a low-speed tester.