Abstract: A computer system includes multiple modules that perform communication via a bus, and abnormality detection circuits that monitor signals on the bus related to communication between the modules to detect a hang-up, wherein each of the abnormality detection circuits is arranged to correspond to a part of the multiple modules, and, when detecting the hang-up, generates and outputs a signal instructing reactivation only of the corresponding module.

Abstract: An interrupt control circuit asserts a remap signal in response to an interrupt request from a low-speed slave to a processor, and reads information stored in an information register of the low-speed slave. The interrupt control circuit writes the read information into a buffer exclusively for interrupt processing. A switch circuit supplies a read access request which is a request from the processor to the information register to the low-speed slave during negation of the remap signal, and supplies the read access request to the buffer via the interrupt control circuit in order to read the information from the buffer during assertion of the remap signal. By accessing to the buffer exclusively for the interrupt processing instead of the information register in response to the read access request from the processor, the interrupt processing time may be shortened.

Abstract: An interrupt control circuit asserts a remap signal in response to an interrupt request from a low-speed slave to a processor, and reads information stored in an information register of the low-speed slave. The interrupt control circuit writes the read information into a buffer exclusively for interrupt processing. A switch circuit supplies a read access request which is a request from the processor to the information register to the low-speed slave during negation of the remap signal, and supplies the read access request to the buffer via the interrupt control circuit in order to read the information from the buffer during assertion of the remap signal. By accessing to the buffer exclusively for the interrupt processing instead of the information register in response to the read access request from the processor, the interrupt processing time may be shortened.

Abstract: A computer system includes multiple modules that perform communication via a bus, and abnormality detection circuits that monitor signals on the bus related to communication between the modules to detect a hang-up, wherein each of the abnormality detection circuits is arranged to correspond to a part of the multiple modules, and, when detecting the hang-up, generates and outputs a signal instructing reactivation only of the corresponding module.