Patents by Inventor Youxin He
Youxin He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966594Abstract: In certain aspects, a memory system includes at least one memory device and a memory controller coupled to the at least one memory device. The memory controller may be configured to determine a current power consumption value indicating total concurrent power consumption of executing a plurality of memory operations in parallel. The memory controller may also be configured to determine an addon power consumption value indicating additional power consumption of executing a subsequent memory operation. The memory controller may be further configured to determine whether a summation of the current and the addon power consumption values exceeds a predetermined power consumption threshold. After determining that the summation of the current and the addon power consumption values does not exceed the predetermined power consumption threshold, the memory controller may be configured to execute the subsequent memory operation in parallel with the plurality of memory operations.Type: GrantFiled: July 23, 2021Date of Patent: April 23, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Feifei Zhu, Youxin He
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Publication number: 20240105273Abstract: The present disclosure provides a method for programing flash memory devices. The method may include programming a selected page of the NAND flash memory device according to programming data. The selected page may include memory cells corresponding to a word line. The programming of the selected page may include programming operations with programming voltages applied on the word line and a read operation performed on the selected page.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Inventor: Youxin HE
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Publication number: 20240071512Abstract: Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to determine that a block of the blocks is an open block based on an open block information, and in response to the block of the blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Inventors: Xiaojiang Guo, Jong Hoon Kang, Youxin He
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Patent number: 11887678Abstract: The present disclosure provides a method for debugging of flash memory devices using NAND self-verification The method can include programming a selected page of the NAND flash memory device according to first and second programming data. The selected page can include a plurality of memory cells corresponding to a word line. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations. Ones of the plurality of verifying operations can be performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the first or second programming data. The method can also include performing self-verification on the selected page to determine whether data stored at the selected page was overwritten and generating a fail indication upon determining that the data stored at the selected page was overwritten.Type: GrantFiled: March 25, 2022Date of Patent: January 30, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventor: Youxin He
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Patent number: 11887679Abstract: The present disclosure provides a method of data protection for a NAND memory. The method can include programming a selected page of the NAND flash memory device according to programming data. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations, with ones of the plurality of verifying operations performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the programming data. The method can also include determining a completion of the programming of the selected page based on each of the plurality of verification operations returning a pass result. The method can also include performing, after the determining, a read operation on the selected page by the NAND flash memory device to self-verify data stored at the selected page according to the programming data.Type: GrantFiled: March 25, 2022Date of Patent: January 30, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventor: Youxin He
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Patent number: 11862250Abstract: Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.Type: GrantFiled: August 27, 2021Date of Patent: January 2, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Xiaojiang Guo, Jong Hoon Kang, Youxin He
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Publication number: 20230230643Abstract: The present disclosure provides a method for debugging of flash memory devices using NAND self-verification The method can include programming a selected page of the NAND flash memory device according to first and second programming data. The selected page can include a plurality of memory cells corresponding to a word line. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations. Ones of the plurality of verifying operations can be performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the first or second programming data The method can also include performing self-verification on the selected page to determine whether data stored at the selected page was overwritten and generating a fail indication upon determining that the data stored at the selected page was overwritten.Type: ApplicationFiled: March 25, 2022Publication date: July 20, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventor: Youxin HE
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Publication number: 20230230644Abstract: The present disclosure provides a method of data protection for a NAND memory. The method can include programming a selected page of the NAND flash memory device according to programming data. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations, with ones of the plurality of verifying operations performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the programming data. The method can also include determining a completion of the programming of the selected page based on each of the plurality of verification operations returning a pass result. The method can also include performing, after the determining, a read operation on the selected page by the NAND flash memory device to self-verify data stored at the selected page according to the programming data.Type: ApplicationFiled: March 25, 2022Publication date: July 20, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventor: Youxin HE
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Publication number: 20230229318Abstract: The present disclosure provides a method of data protection for a NAND memory. The method includes programming first and second pages of a NAND flash memory device according to programming data such that data stored in the first and second pages are redundant. The programming of the first and second pages includes a plurality of programming operations using a plurality of programming voltages and a plurality of verifying operations to determine whether programmed memory cells of the first page have threshold voltage levels according to the programming data. The method also includes determining a completion of the programming of the first and second pages based on each of the plurality of verification operations returning a pass result. The method also includes performing, after the determining, a read operation on the second page by the NAND flash memory device to self-verify the data stored at the second page.Type: ApplicationFiled: March 25, 2022Publication date: July 20, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventor: Youxin HE
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Publication number: 20220382466Abstract: In certain aspects, a memory system includes at least one memory device and a memory controller coupled to the at least one memory device. The memory controller may be configured to determine a current power consumption value indicating total concurrent power consumption of executing a plurality of memory operations in parallel. The memory controller may also be configured to determine an addon power consumption value indicating additional power consumption of executing a subsequent memory operation. The memory controller may be further configured to determine whether a summation of the current and the addon power consumption values exceeds a predetermined power consumption threshold. After determining that the summation of the current and the addon power consumption values does not exceed the predetermined power consumption threshold, the memory controller may be configured to execute the subsequent memory operation in parallel with the plurality of memory operations.Type: ApplicationFiled: July 23, 2021Publication date: December 1, 2022Inventors: Feifei Zhu, Youxin He
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Publication number: 20220382467Abstract: In certain aspects, a memory system may include at least one memory device and a memory controller coupled to the at least one memory device. Each memory device may include an array of memory cells and a control logic coupled to the array of memory cells. The memory controller and the control logic of the memory device may be powered by a first power source having a first predetermined power consumption threshold. The array of memory cells of the memory device may be powered by a second power source having a second predetermined power consumption threshold.Type: ApplicationFiled: July 23, 2021Publication date: December 1, 2022Inventors: Feifei Zhu, Youxin He
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Publication number: 20220293187Abstract: Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.Type: ApplicationFiled: August 27, 2021Publication date: September 15, 2022Inventors: Xiaojiang GUO, Jong Hoon Kang, Youxin He