Patents by Inventor Yu-Chang Jong
Yu-Chang Jong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8004038Abstract: A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.Type: GrantFiled: May 22, 2006Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsing-Yi Chien, Yu-Chang Jong, Te-Yin Hsia, Ruey-Shin Liu
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Publication number: 20100289057Abstract: An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).Type: ApplicationFiled: May 11, 2010Publication date: November 18, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Song SHEU, Jian-Hsing LEE, Yu-Chang JONG, Chun-Chien TSAI
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Patent number: 7808069Abstract: A high-voltage Schottky diode including a deep P-well having a first width is formed on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.Type: GrantFiled: December 31, 2008Date of Patent: October 5, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Dah-Chuen Ho, Chien-Shao Tang, Yu-Chang Jong, Zhe-Yi Wang
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Publication number: 20100164050Abstract: A high-voltage Schottky diode including a deep P-well having a first width is fanned on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dah-Chuen HO, Chien-Shao TANG, Yu-Chang JONG, Zhe-Yi WANG
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Publication number: 20090294865Abstract: An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.Type: ApplicationFiled: May 27, 2008Publication date: December 3, 2009Inventors: Chien-Shao Tang, Dah-Chuen Ho, Yu-Chang Jong, Zhe-Yi Wang, Yuh-Hwa Chang, Yogendra Yadav
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Patent number: 7608889Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.Type: GrantFiled: September 28, 2007Date of Patent: October 27, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Dah-Chuen Ho, Chien-Shao Tang, Zhe-Yi Wang, Yu-Chang Jong
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Patent number: 7521741Abstract: A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 ?m. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.Type: GrantFiled: November 6, 2006Date of Patent: April 21, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chang Jong, Ruey-Hsin Liu, Yueh-Chiou Lin, Shun-Liang Hsu, Chi-Hsuen Chang, Te-Yin Hsia
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Publication number: 20090085112Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dah-Chuen Ho, Chien-Shao Tang, Zhe-Yi Wang, Yu-Chang Jong
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Patent number: 7482662Abstract: A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.Type: GrantFiled: October 30, 2006Date of Patent: January 27, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bau Wu, Shun-Liang Hsu, You-Kuo Wu, Yu-Chang Jong
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Patent number: 7384802Abstract: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.Type: GrantFiled: May 22, 2006Date of Patent: June 10, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hsing Lee, Yu-Chang Jong
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Patent number: 7372083Abstract: A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW) region, a second source/drain region doped with a p-type impurity in a high voltage n-well (HVNW) region wherein the HVPW region and HVNW region physically contact each other, a field region substantially underlying a gate dielectric, and a first heavily doped n-type (N+) region in the HVPW region and contacting the first source/drain region. The device further includes an N+ buried layer underlying the HVPW region and the HVNW region and a p-type substrate underlying the N+ buried layer. The device has robust performance for both forward and reverse mode ESD.Type: GrantFiled: August 9, 2005Date of Patent: May 13, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hsing Lee, Yu-Chang Jong
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Publication number: 20080073745Abstract: A high-voltage semiconductor structure includes a high-voltage well region overlying a substrate, an isolation region extending from a top surface of the high-voltage well region into the high-voltage well region, a low-voltage well region having at least a portion underlying and adjoining the isolation region wherein the low-voltage well region is inside of and of a same conductivity type as the high-voltage well region, a gate dielectric on the high-voltage well region, a gate electrode on the gate dielectric, and a source/drain region of the same conductivity type as the high-voltage well region, wherein the source/drain region is spaced apart from a channel region by the isolation region.Type: ApplicationFiled: September 25, 2006Publication date: March 27, 2008Inventors: Chien-Shao Tang, Tsung-Yi Huang, David Ho, Zhe-Yi Wang, Yu-Chang Jong
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Publication number: 20080001189Abstract: A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 ?m. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.Type: ApplicationFiled: November 6, 2006Publication date: January 3, 2008Inventors: Yu-Chang Jong, Ruey-Hsin Liu, Yueh-Chiou Lin, Shun-Liang Hsu, Chi-Hsuen Chang, Te-Yin Hsia
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Publication number: 20070267693Abstract: A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.Type: ApplicationFiled: May 22, 2006Publication date: November 22, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsing-Yi Chien, Yu-Chang Jong, Ruey-Hsin Liu, Te-Yin Hsia
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Publication number: 20070187766Abstract: A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.Type: ApplicationFiled: October 30, 2006Publication date: August 16, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Bau Wu, Shun-Liang Hsu, You-Kuo Wu, Yu-Chang Jong
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Publication number: 20070034956Abstract: A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW) region, a second source/drain region doped with a p-type impurity in a high voltage n-well (HVNW) region wherein the HVPW region and HVNW region physically contact each other, a field region substantially underlying a gate dielectric, and a first heavily doped n-type (N+) region in the HVPW region and contacting the first source/drain region. The device further includes an N+ buried layer underlying the HVPW region and the HVNW region and a p-type substrate underlying the N+ buried layer. The device has robust performance for both forward and reverse mode ESD.Type: ApplicationFiled: August 9, 2005Publication date: February 15, 2007Inventors: Jian-Hsing Lee, Yu-Chang Jong
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Publication number: 20070037355Abstract: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.Type: ApplicationFiled: May 22, 2006Publication date: February 15, 2007Inventors: Jian-Hsing Lee, Yu-Chang Jong
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Patent number: 7129559Abstract: A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.Type: GrantFiled: April 9, 2004Date of Patent: October 31, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bau Wu, Shun-Liang Hsu, You-Kuo Wu, Yu-Chang Jong
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Patent number: 7081662Abstract: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.Type: GrantFiled: August 9, 2005Date of Patent: July 25, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hsing Lee, Yu-Chang Jong
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Publication number: 20060108641Abstract: Provided are a device and method for its manufacture. In one example, the device includes a semiconductor substrate that includes a well region formed using a first-type dopant. First and second doped regions are formed in the well region using a second-type dopant, and the first and second doped regions are separated from each other by a dielectric isolation feature. A third doped region is formed in the well region using the first-type dopant and positioned under the dielectric isolation feature and between the first doped region and the second doped region. The third doped region has a dopant concentration higher than that of the well region.Type: ApplicationFiled: November 19, 2004Publication date: May 25, 2006Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chang Jong, Chen-Bau Wu, Ruey-Hsing Liu, Kuo-Ming Wu