Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: An information handling system includes a display panel having an active area that generates visual images and an inactive area disposed outside the active area. The inactive area having an alignment mark that is invisible to a naked eye.

Abstract: A method for detecting defects on a wafer including the steps of obtaining a reference image of a chip pattern formed on a reference wafer, using a computer algorithm to analyze the reference image to produce a division map for the chip pattern; setting respective thresholds for divisions of the division map, obtaining a comparison data between a test image of the chip pattern formed on a test wafer and the reference image, using the division map and the thresholds to examine the comparison data to identify a defect in the test image.

Abstract: A modulation device including a plurality of electronic elements, at least one first signal line and a first driving circuit is provided. The at least one first signal line is respectively electrically connected to at least one of the electronic elements. The first driving circuit is electrically connected to the at least one first signal line. The first driving circuit provides a first signal to at least one of the at least one first signal line. The first signal includes a first pulse. The first pulse includes a first section and a second section closely adjacent to the first section.

Abstract: An antenna module is disposed to an electronic device includes a fixed member, a rotating component, a reflector, a director, and an antenna unit. The electronic device includes a first body and a second body. The first body has a first surface and a second surface. The fixed member is disposed to the first body fixedly. The rotating component is connected to the fixed member rotatably. The reflector and the director are disposed to the rotating component. The antenna unit is disposed to the first body and between the reflector and the director. When the first body and the second body rotate relative to each other, the reflector is located between the antenna unit and one of the first surface and the second surface, and the director is located between the antenna unit and another one of the first surface and the second surface.

Abstract: A piezoelectric material composite membrane acoustic component with broadband and high sound quality comprises a vibrating membrane which is an electrically conductive membrane, a supporting frame having a hollow portion penetrating the supporting frame, a piezoelectric plat set including a first-piezoelectric-plate and a second-piezoelectric-plate formed on and electrically connected to the first-piezoelectric-plate and an AC power. A fixing portion of the vibrating membrane is fixed by the supporting frame. Each of the first-piezoelectric-plate and the second-piezoelectric-plate includes a top-electrode-layer, a piezoelectric-layer and a bottom-electrode-layer. The bottom-electrode-layer of the first-piezoelectric-plate is fixed on and electrically connected to a piezoelectric-plate fixing portion of the vibrating membrane. A spacing portion of the vibrating membrane is between the fixing portion and the piezoelectric-plate fixing portion.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: Container data sharing is provided. A second container of a cluster of containers is started to process a service request in response to detecting a failure of a first container processing the service request. The service request and data generated by the first container that failed stored on a physical external memory device is accessed. The service request and the data generated by the first container that failed is loaded on the second container from the physical external memory device via a dedicated hardware link for high-speed container failure recovery.

Abstract: This disclosure provides a lens assembly that has an optical path and includes a lens element and a light-blocking membrane layer. The lens element has an optical portion, and the optical path passes through the optical portion. The light-blocking membrane layer is coated on the lens element and adjacent to the optical portion. The light-blocking membrane layer has a distal side and a proximal side that is located closer to the optical portion than the distal side. The proximal side includes two extension structures and a recessed structure. Each of the extension structures extends along a direction away from the distal side, and the extension structures are not overlapped with each other in a direction in parallel with the optical path. The recessed structure is connected to the extension structures and recessed along a direction towards the distal side.

Abstract: A circuit board includes a substrate and a metallic layer. A first area and at least one second area are defined on a portion of the substrate, the second area is located outside the first area. The metallic layer includes first test lines disposed on the first area and second test lines disposed on the second area. A first test pad of each of the first test lines has a first width, and a second test pad of each of the second test lines has a second width. The second width is greater than the first width such that probes of an electrical testing tool can contact the first and second test pads on the circuit board correctly during electrical testing.

Abstract: An electronic device and a forming method thereof are provided. The electronic device includes a substrate, a metal layer, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer. The metal layer is disposed on the substrate and includes a sensing line and a drain electrode. The first insulating layer is disposed on the metal layer. The first conductive layer is disposed on the first insulating layer and includes a touch electrode. The second insulating layer is disposed on the first conductive layer. The second conductive layer is disposed on the second insulating layer and includes a conductive pattern. The conductive pattern is electrically connected to the sensing line and the touch electrode.

Abstract: A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A portion of the photoresist layer is exposed, using a mask, to a radiation. The photoresist layer is treated, using a basic gas. The photoresist layer is developed to form a patterned photoresist layer over the substrate.

Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.

Abstract: A method for fabricating a semiconductor structure includes: providing a substrate and a dielectric layer on the substrate; and forming an etching mask on the dielectric layer; and etching the dielectric layer using the etching mask to form at least one opening therein. The etching mask includes: a hard mask layer, a photoresist layer, and a hexamethyldisilazane (HMDS) layer. The photoresist layer is located over the hard mask layer, and the HMDS layer is located between the hard mask layer and the photoresist layer.

Abstract: A system and method for fixing DRC violations includes receiving a layout pattern having a design rule check (DRC) violation therein, determining that the layout pattern is an inlier based upon a comparison of the layout pattern with a plurality of previously analyzed layout patterns. The comparison may be performed by an anomaly detection algorithm. The system and method may also include selecting a recipe from a pool of recipes previously applied to the plurality of previously analyzed layout patterns for fixing the DRC violation in the layout clip upon determining that the layout pattern is an inlier.

Abstract: An electronic device including a backlight module is disclosed. The backlight module includes: a substrate; a plurality of light emitting diodes disposed on the substrate, wherein the plurality of light emitting diodes are blue light emitting diodes; a protection layer disposed on the substrate and covering the plurality of light emitting diodes; and a color conversion element, disposed on the plurality of light emitting diodes.

Abstract: A system and method for fixing DRC violations includes receiving a layout pattern having a design rule check (DRC) violation therein, determining that the layout pattern is an inlier based upon a comparison of the layout pattern with a plurality of previously analyzed layout patterns. The comparison may be performed by an anomaly detection algorithm. The system and method may also include selecting a recipe from a pool of recipes previously applied to the plurality of previously analyzed layout patterns for fixing the DRC violation in the layout clip upon determining that the layout pattern is an inlier.