Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: An immersion cooling system including a rack and at least one immersion cooling module is provided. The immersion cooling module includes a chassis and a condensation pipeline. The chassis is slidably disposed on the rack and is adapted to accommodate a coolant. At least one heat generating component is adapted to be disposed in the chassis to be immersed in the liquid coolant. The condensation pipeline is disposed in the chassis and is located above the liquid coolant. In addition, an electronic apparatus having the immersion cooling system is also provided.

Abstract: An immersion cooling system including a rack and at least one immersion cooling module is provided. The immersion cooling module includes a chassis and a condensation pipeline. The chassis is slidably disposed on the rack and is adapted to accommodate a coolant. At least one heat generating component is adapted to be disposed in the chassis to be immersed in the liquid coolant. The condensation pipeline is disposed in the chassis and is located above the liquid coolant. In addition, an electronic apparatus having the immersion cooling system is also provided.

Abstract: A hybrid video decoder has a hardware decoding circuit, a software decoding circuit, and a meta-data access system. The hardware decoding circuit deals with a first portion of a video decoding process for at least a portion of a frame, wherein the first portion of the video decoding process includes entropy decoding. The software decoding circuit deals with a second portion of the video decoding process. The meta-data access system manages meta data transferred between the hardware decoding circuit and the software decoding circuit.

Abstract: A hybrid video decoding apparatus has a hardware entropy decoder and a storage device. The hardware entropy decoder performs hardware entropy decoding to generate an entropy decoding result of a picture. The storage device has a plurality of storage areas allocated to buffer a plurality of entropy-decoded partial data, respectively, and is further arranged to store position information indicative of storage positions of the entropy-decoded partial data in the storage device. The entropy-decoded partial data are derived from the entropy decoding result of the picture, and are associated with a plurality of portions of the picture, respectively.

Abstract: A memory pool management method includes: allocating a plurality of memory pools in a memory device according to information about a plurality of computing units, wherein the computing units are independently executed on a same processor; and assigning one of the memory pools to one of the computing units, wherein at least one of the memory pools is shared among different computing units of the computing units.

Abstract: A computing system includes a plurality of processing circuits and a storage device. The processing circuits have at least a first processing circuit and a second processing circuit. The storage device is shared between at least the first processing circuit and the second processing circuit. The first processing circuit performs a whole cache flush operation to prepare exchange data in the storage device. The second processing circuit gets the exchange data from the storage device.