Patents by Inventor Yu-Cheng Hsu

Yu-Cheng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10305979
    Abstract: An efficient cloning mechanism is provided for a distributed storage environment, where, for example, a private cloud computing environment and a public cloud computing environment are included in a hybrid cloud computing environment (on-premise object storage to off-premise computation resources), to improve computation workloads. The disclosed algorithm forms an efficient cloning mechanism in a hybrid storage environment where the read/write speed of data from the disk is not limited by its angular velocity.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sasikanth Eda, Deepak R. Ghuge, Yu-Cheng Hsu, Sandeep R. Patil
  • Publication number: 20190114226
    Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming units; writing a second data into a second physical programming units; encoding by using the first data without using the second data to generate a first encoded data; encoding by using the second data and a first sub-data of the first data to generate a second encoded data; and writing the first encoded data and the second encoded data into a third physical programming unit and a fourth physical programming unit.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 18, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Chih-Kang Yeh, Yu-Cheng Hsu, Szu-Wei Chen
  • Publication number: 20190094960
    Abstract: A gaze detection, identification and control method includes steps of providing a portable electronic device, performing a continuous image capture on a user through an image capture unit of the portable electronic device to sequentially obtain an initial image and a plurality of detected images, detecting and defining a gaze position of the user according to the initial image, identifying a change amount and a change direction of the gaze position of the user according to the detected images, and sending a control command according to the change amount and the change direction. Therefore, the advantages of easy recognition and time-saving are achieved.
    Type: Application
    Filed: December 13, 2017
    Publication date: March 28, 2019
    Inventors: Huang-Chih Chen, Yueh-Hsiang Chen, Yu-Cheng Hsu
  • Publication number: 20190088336
    Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: when first data is read from a first upper physical programming unit of a first physical programming unit group by using a second voltage selected from a first read voltage group, and a first error bit count of the first data is not greater than a first error bit count threshold, recording the second voltage; when a second data is read from a first lower physical programming unit of a second physical programming unit group by using a fourth voltage selected from a second read voltage group, and a second error bit count of the second data is not greater than a second error bit count threshold, recording the fourth voltage; generating a lookup table according to the second voltage and the fourth voltage; and performing a decoding operation according to the lookup table.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 21, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Yu-Siang Yang
  • Publication number: 20190050268
    Abstract: The present disclosure provides a system and method for automatically composing resources in a data center using a management application. The management application can communicate with a data center management software to collect information of computer resource, storage resource, and network resource of the data center. Based at least upon the network resource information of the data center, the management application can generate a network topology of the data center. In response to receiving a request from a specific user, the management application can compose suitable resources of the data center to match the request.
    Type: Application
    Filed: November 8, 2017
    Publication date: February 14, 2019
    Inventors: Kun-Hu TSAI, Ching-Chih SHIH, Yu-Cheng HSU
  • Publication number: 20180374543
    Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.
    Type: Application
    Filed: August 31, 2017
    Publication date: December 27, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Tien-Ching Wang
  • Publication number: 20180300950
    Abstract: A 3D model reconstruction method includes: providing, by one or more laser emitters, laser beams; capturing, by a depth camera on an electronic device, a depth data of a target object when that the electronic device moves around the target object; detecting, by one or more light sensors on the electronic device, the laser beams emitted by the one or more laser emitters to obtain a camera pose initial value of the depth camera accordingly; and performing, by a processing circuit, a 3D reconstruction of the target object using the depth data based on the camera pose initial value to output a 3D model of the target object.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 18, 2018
    Inventors: Jui-Hsuan CHANG, Yu-Cheng HSU, Cheng-Yuan SHIH, Sheng-Yen LO, Hung-Yi YANG
  • Patent number: 10074433
    Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming unit of a first physical programming unit group among a plurality of physical programming unit groups; writing a second data into a second physical programming unit of a second physical programming unit group among the plurality of physical programming unit groups; encoding the first data and the second data to generate an encoded data; and writing the encoded data into a third physical programming unit group among the plurality of physical programming unit groups.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 11, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Cheng Hsu, Wei Lin, Yu-Siang Yang
  • Patent number: 10067824
    Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: September 4, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Shao-Wei Yen, Tien-Ching Wang, Yu-Hsiang Lin, Kuo-Hsin Lai, Li-Chun Liang
  • Publication number: 20180136841
    Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units and a memory control circuit unit and a memory storage apparatus using the same are provided. Each of the physical erasing units has a plurality of physical programming unit sets, and each of the physical programming unit sets has a plurality of physical programming unit. The method includes receiving data and arranging the data to generate a first data stream and a second data stream. The method also includes encoding the first data stream and the second data stream to generate a third data stream, and issuing a programming command sequence to write the first data stream, the second data stream and the third data stream respectively into a first physical programming unit, a second physical programming unit and a third physical programming unit of a physical programming unit set.
    Type: Application
    Filed: January 23, 2017
    Publication date: May 17, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
  • Patent number: 9971520
    Abstract: Provided are a method, system, and computer program product for processing read and write requests in a storage controller. A host adaptor in the storage controller receives a write request from a host system for a storage address in a storage device. The host adaptor sends write information indicating the storage address updated by the write request to a device adaptor in the storage controller. The host adaptor writes the write data to a cache in the storage controller. The device adaptor indicates the storage address indicated in the write information to a modified storage address list stored in the device adaptor, wherein the modified storage address list indicates modified data in the cache for storage addresses in the storage device.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: May 15, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence Y. Chiu, Yu-Cheng Hsu, Sangeetha Seshadri
  • Patent number: 9972390
    Abstract: The memory programming method includes: applying a first programming parameter set to program first data stream into a first physical programming unit, and the first physical programming unit is composed of memory cells at intersections between a first bit line string of a physical erasing unit and a first word line layer of the physical erasing unit. The memory programming method further includes applying a second programming parameter set to program the first data stream into all of the memory cells of the first physical programming unit again after completely programming the first data stream into all of the memory cells of the first physical programming unit.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: May 15, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
  • Patent number: 9947417
    Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: programming data into a plurality of memory cells of a rewritable non-volatile memory module; determining whether a storage state of the data conforms with a first condition or a second condition based on a default bias range and a threshold voltage distribution of the memory cells storing the data; performing a first operation if the storage state of the data conforms with the first condition; and performing a second operation if the storage state of the data conforms with the second condition. Accordingly, the probability of misidentifying the valid data as the invalid data may be reduced.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: April 17, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu
  • Publication number: 20180101317
    Abstract: The memory programming method includes: applying a first programming parameter set to program first data stream into a first physical programming unit, and the first physical programming unit is composed of memory cells at intersections between a first bit line string of a physical erasing unit and a first word line layer of the physical erasing unit. The memory programming method further includes applying a second programming parameter set to program the first data stream into all of the memory cells of the first physical programming unit again after completely programming the first data stream into all of the memory cells of the first physical programming unit.
    Type: Application
    Filed: November 24, 2016
    Publication date: April 12, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
  • Patent number: 9892799
    Abstract: A read voltage tracking method, a memory storage device and a memory control circuit unit are provided. The method includes obtaining a plurality of test read voltages corresponding to a plurality of voltage adjustment values, and obtaining an optimal read voltage according to the voltage adjustment values. The step of obtaining the test read voltages includes obtaining a second test read voltage by adjusting a first test read voltage according to a first voltage adjustment value, and obtaining a third test read voltage by adjusting the second test read voltage according to a second voltage adjustment value, and the first test read voltage is a preset test read voltage, the first voltage adjustment value is a preset voltage adjustment value, and the first voltage adjustment value is different from the second voltage adjustment value.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: February 13, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, An-Cheng Liu
  • Patent number: 9851933
    Abstract: There is a method and system for capability-based resource allocation in a software-defined environment that performs the following steps (not necessarily in the following order): (i) determining a set of capability characteristics for a plurality of workload resources within a software-defined environment; (ii) determining a set of workload components for a specified workload; and (iii) identifying a set of workload resources from the plurality of workload resources to allocate to the specified workload based, at least in part, on the set of capability characteristics corresponding to each workload within the set of workload resources. A workload component of the set of workload components has a unique set of workload characteristics.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Brad L. Brech, Scott W. Crowder, Hubertus Franke, Jeffrey A. Frey, Nagui Halim, Matt R. Hogstrom, Yu-Cheng Hsu, Dilip D. Kandlur, Chung-Sheng Li, David B. Lindquist, Stefan Pappe, Pratap C. Pattnaik, Balachandar Rajaraman, Radha P. Ratnaparkhi, Renato J. Recio, Rodney A. Smith, Michael D. Williams
  • Patent number: 9812194
    Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining usage state information of first memory cells; reading second memory cells by a first read voltage level to obtain at least one first bit and reading the second memory cells by a second read voltage level to obtain at least one second bit according to the usage state information, wherein the first bit corresponds to a storage state of a first part of memory cells among the second memory cells, the second bit corresponds to a storage state of a second part of memory cell among the second memory cells, and the first read voltage level is different from the second read voltage level; and decoding third bits including the first bit and the second bit. Therefore, a decoding efficiency can be improved.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: November 7, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
  • Patent number: 9785561
    Abstract: An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kevin J. Ash, Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Yu-Cheng Hsu, Xiaoyu Hu, Joseph S. Hyde, II, Roman A. Pletka, Alfred E. Sanchez
  • Patent number: 9563508
    Abstract: The present disclosure provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes physical programming units, each of which includes multiple bits. The memory management method includes: identifying a first physical programming unit by applying a predetermined read voltage, where the first physical programming unit is identified as in a fully-erased status; identifying a second and a third physical programming units which are programmed before the first physical programming unit; acquiring status data of the second and the third physical programming unit; computing a difference of the status data between the second and the third physical programming unit; if the difference is larger than a threshold, identifying the second physical programming unit as in a program failure status.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 7, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, An-Cheng Liu, Siu-Tung Lam
  • Patent number: 9530509
    Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the first data into a first lower physical programming unit; receiving second data; in response to the second data to be programmed into a first upper physical programming unit corresponding to the first lower physical programming unit, performing a first data obtaining operation which does not include reading the first lower physical programming unit by using a default read voltage; and programming the second data into the first upper physical programming unit according to the third data obtained through the first data obtaining operation.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: December 27, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai, Yu-Cheng Hsu, Chi-Heng Yang