Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

Abstract: A vibration-proof holder applicable to a communications/navigation device for vehicle use is provided, characterized by the use of a gap-detecting unit to detect position variations of the communications/navigation device, and an electromagnetic control unit to adjust magnetic intensity of magnetic bodies fixedly installed in the vehicle, wherein first and second magnetic bodies are limited to remain in the same track and to face one another with the same magnetic polar end thereof, such that the communications/navigation device can return to its initial position to achieve the vibration-proof effect.

Abstract: A clock data recovery (CDR) circuit that can be used for recovering data from a high-speed serial transmission using components that operate at a fraction of the data speed. The CDR consists of a phase detector, an averaging circuit and a phase interpolator. The phase detector samples each data bit at its midpoint and at its transitional region and then compares the two samples to determine whether the sampling clock, which is generated by a phase interpolator, is leading or lagging the data stream. The averaging circuit filters out the high frequency jitters in the phase detector output and then passes the filtered signals on to the phase interpolator for phase selection. The phase interpolator uses the filtered signals from the averaging circuit as a guide in the selection of an output clock phase that minimizes the phase difference between the output clock and the incoming data.

Abstract: A phase interpolator circuit that produces 2m phase resolution elements using a control signal that has less than m bits. The circuit combines the function of a divide-by-N circuit with a phase interpolation circuit enabled by the use of a higher-speed clock as an input. By performing phase interpolation at a high speed and then slowing down the speed for the subsequent circuits, the phase resolution increases and fewer control bits are required.

Abstract: A digital-to-analog converter (DEC) is useful for driving both SVGA display monitors and NTSC TV monitors. The DAC converts 8-bit digital signals to analog voltage for SVGA, but converts 9-bit signals to a wider range of analog voltages for NTSC. Instead of doubling a number of current sources from 255 to 511 for 9-bit conversions, a single least-significant-bit (LSB) current source is added for 9-bit mode. The LSB current source adds one-half of the current that the other current sources do. The LSB current source is disabled for 8-bit mode. The current from the other current sources is doubled for 9-bit mode by adjusting the bias voltage. The bias voltage for p-channel transistors in all the current sources is lowered for 9-bit mode by a bias generator. The bias generator compares a voltage across an external resistor to a band-gap reference and adjusts the bias voltage until the voltage drop across the resistor matches the band-gap reference.

Abstract: A digital-to-analog converter (DAC) is useful for driving both SVGA display monitors and NTSC TV monitors. The DAC converts 8-bit digital signals to analog voltage for SVGA, but converts 9-bit signals to a wider range of analog voltages for NTSC. Instead of doubling a number of current sources from 255 to 511 for 9-bit conversions, a single least-significant-bit (LSB) current source is added for 9-bit mode. The LSB current source adds one-half of the current that the other current sources do. The LSB current source is disabled for 8-bit mode. The current from the other current sources is doubled for 9-bit mode by adjusting the bias voltage. The bias voltage for p-channel transistors in all the current sources is lowered for 9-bit mode by a bias generator. The bias generator compares a voltage across an external resistor to a band-gap reference and adjusts the bias voltage until the voltage drop across the resistor matches the band-gap reference.