Patents by Inventor Yu-Chi Chuang
Yu-Chi Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240150896Abstract: A high-speed, uniform and high-quality surface treatment apparatus is described. The surface treatment apparatus includes a fixed hollow cylindrical chamber body and a rotatable polygonal prism inside the chamber body. Several flat-substrate holders are symmetrically disposed on the prism surface. The substrate holders revolve as the prism rotates. On the fixed chamber wall, several gas inlet channels, pumping channels and processing units are installed according to the symmetric configuration of the substrate holders. Then, as the substrate holders revolve, the surface treatment processes will occur periodically, including the injection of gas reactants into, the activation of gases in, and the pumping of after-reaction gases out of the processing spaces, defined by the substrate holders and the chamber wall. The substrates will therefore undergo many cycles of periodic surface treatment processes.Type: ApplicationFiled: November 7, 2022Publication date: May 9, 2024Inventors: Ming-Yueh CHUANG, Chau-Nan HONG, Yu-Chi CHANG
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Publication number: 20240079493Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Inventors: GUAN-QI CHEN, CHEN CHI HSIAO, KUN-TSANG CHUANG, FANG YI LIAO, YU SHAN HUNG, CHUN-CHIA CHEN, YU-SHAN HUANG, TUNG-I LIN
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Patent number: 11923428Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.Type: GrantFiled: April 20, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chi Pan, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11914429Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.Type: GrantFiled: March 9, 2023Date of Patent: February 27, 2024Assignee: Acer IncorporatedInventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee
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Patent number: 8850169Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.Type: GrantFiled: July 1, 2013Date of Patent: September 30, 2014Assignee: Marvell International Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Patent number: 8799929Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.Type: GrantFiled: April 15, 2013Date of Patent: August 5, 2014Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Publication number: 20130247072Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.Type: ApplicationFiled: April 15, 2013Publication date: September 19, 2013Applicant: Marvell World Trade Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Patent number: 8539212Abstract: Systems, apparatuses, and methods for determinative branch prediction indexing are described herein. The determinative branch prediction indexing method includes receiving a program counter address for a branch instruction, dynamically selecting a branch indexing scheme from a plurality of branch indexing schemes, and generating a branch prediction index based at least in part on selected branch indexing scheme and the program counter address. Other embodiments may be described and claimed.Type: GrantFiled: August 31, 2012Date of Patent: September 17, 2013Assignee: Marvell International Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Patent number: 8478971Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.Type: GrantFiled: December 19, 2011Date of Patent: July 2, 2013Assignee: Marvell International Ltd.Inventors: Jack Kang, Yu-Chi Chuang, Hsi-Cheng Chu
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Patent number: 8473728Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.Type: GrantFiled: May 24, 2012Date of Patent: June 25, 2013Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Patent number: 8424021Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.Type: GrantFiled: October 21, 2011Date of Patent: April 16, 2013Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Publication number: 20120239915Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.Type: ApplicationFiled: May 24, 2012Publication date: September 20, 2012Inventors: Jack Kang, His-Cheng Chu, Yu-Chi Chuang
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Patent number: 8261049Abstract: Systems, apparatuses, and methods for determinative branch prediction indexing are described herein. The determinative branch prediction indexing method includes receiving a program counter address for a branch instruction, dynamically selecting a branch indexing scheme from a plurality of branch indexing schemes, and generating a branch prediction index based at least in part on selected branch indexing scheme and the program counter address. Other embodiments may be described and claimed.Type: GrantFiled: April 9, 2008Date of Patent: September 4, 2012Assignee: Marvell International Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Patent number: 8190866Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.Type: GrantFiled: January 10, 2011Date of Patent: May 29, 2012Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Publication number: 20120036518Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.Type: ApplicationFiled: October 21, 2011Publication date: February 9, 2012Inventors: Jack Kang, Yu-Chi Chuang
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Patent number: 8082427Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.Type: GrantFiled: July 7, 2010Date of Patent: December 20, 2011Assignee: Marvell International Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Patent number: 8046775Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.Type: GrantFiled: July 9, 2007Date of Patent: October 25, 2011Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Patent number: 7941643Abstract: A system, apparatus and method for an interleaving multi-thread processing device are described herein. The multi-thread processing device includes an execution block to execute instructions and a fetch block to fetch and issue instructions, interleavingly, of a first instruction execution thread and at least one other instruction execution thread. The fetch block includes at least one program counter, which is allocable and/or corresponds to each instruction execution thread.Type: GrantFiled: July 9, 2007Date of Patent: May 10, 2011Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Publication number: 20110107062Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.Type: ApplicationFiled: January 10, 2011Publication date: May 5, 2011Inventors: Jack Kang, His-Cheng Chu, Yu-Chi Chuang
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Patent number: D1027976Type: GrantFiled: May 24, 2021Date of Patent: May 21, 2024Assignee: VIVOTEK INC.Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung