Patents by Inventor Yu-Chi Li

Yu-Chi Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240158309
    Abstract: The invention provides a material surface treatment equipment, which is applied to a material substrate. The material surface treatment equipment includes a surface treatment device and at least one waveguide device. The surface treatment device is used to carry the material substrate to perform a surface treatment process. Each waveguide device is used for introducing electromagnetic waves to the material substrate to assist in performing the surface treatment process. Through the introduction of electromagnetic waves, the surface treatment process of the material substrate is easy to perform and can achieve the strengthening effect.
    Type: Application
    Filed: December 15, 2022
    Publication date: May 16, 2024
    Inventors: TIEN-HSI LEE, JUN-HUANG WU, YU-SHENG CHIOU, SHU-CHENG LI, WEI-CHI HUANG, HSIN CHEN
  • Patent number: 11984419
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Publication number: 20240151642
    Abstract: A terahertz wave detection chip includes a substrate and at least one detection structure. The detection structure is disposed on a surface of the substrate. The detection structure includes a metamaterial layer and a hydrophilic layer, and the hydrophilic layer is disposed on the metamaterial layer.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 9, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Tai LI, Kao-Chi LIN, Cho-Fan HSIEH, Teng-Chun WU
  • Patent number: 11907633
    Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Publication number: 20220382948
    Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Patent number: 11494543
    Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Patent number: 11477187
    Abstract: In an approach for an API key access authorization, a processor receives a transaction identity, a part of a token, and an API key identity attribute from a server. The transaction identity is generated in the server associated with generating the token. A processor receives a request from a client with the transaction identity for the part of the token. A processor looks up a transaction table via the transaction identity as an index. The transaction identity is associated with the part of the token and the API key identity attribute. A processor retrieves a client identity attribute through a second server via an IP address of the client. The second server registers the client. A processor matches a policy via the API key identity attribute and the client identity attribute. A processor sends the part of the token to the client.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Yi Fei He, Gang Tang, Hua Hong Wang, Xiaoli Xu, Yu Chi Li
  • Publication number: 20210281555
    Abstract: In an approach for an API key access authorization, a processor receives a transaction identity, a part of a token, and an API key identity attribute from a server. The transaction identity is generated in the server associated with generating the token. A processor receives a request from a client with the transaction identity for the part of the token. A processor looks up a transaction table via the transaction identity as an index. The transaction identity is associated with the part of the token and the API key identity attribute. A processor retrieves a client identity attribute through a second server via an IP address of the client. The second server registers the client. A processor matches a policy via the API key identity attribute and the client identity attribute. A processor sends the part of the token to the client.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 9, 2021
    Inventors: Yi Fei He, Gang Tang, Hua Hong Wang, Xiaoli Xu, Yu Chi Li
  • Publication number: 20200285797
    Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Patent number: 10685162
    Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Publication number: 20190121931
    Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Patent number: 10163883
    Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Publication number: 20170365592
    Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Application
    Filed: June 15, 2016
    Publication date: December 21, 2017
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Publication number: 20160291407
    Abstract: A display device includes a a display module and backlight module for providing light required by the display module. The backlight module includes a light source assembly and a reflector. The reflector includes a bottom plate and a plurality of side plates coupled to the bottom plate. At least one of the plurality of side plates includes at least one reflectance adjustment member to adjust a light reflectance value (LRV) of the at least one of the side plates.
    Type: Application
    Filed: July 27, 2015
    Publication date: October 6, 2016
    Inventor: YU-CHI LI
  • Publication number: 20160216559
    Abstract: A backlight module for providing backlight to a display panel includes a plurality of light sources, a plurality of optical elements corresponding to the light sources, and a circuit board. The circuit board is electrically connected to the light sources, and defines a plurality of predetermined regions corresponding to the optical elements. Each of the predetermined regions includes a plurality of patterns on an upper surface of the circuit board. The patterns in the same predetermined region form a series of concentric rings centered on the corresponding light source. The patterns adjusts a transmitting parameter of the light to be reflected by the corresponding predetermined region.
    Type: Application
    Filed: July 16, 2015
    Publication date: July 28, 2016
    Inventors: IVAN DE JESUS CAZAREZ LOPEZ, CHIA-CHUN FANG, YU-CHI LI
  • Patent number: 8807383
    Abstract: A gasoline storage device, which is regulated to prevent gasoline from vaporizing, and is fabricated from a soft gasoline bag made from soft material that has been processed and coated on both sides so as to be resistant against gasoline and the majority of chemical liquids. The soft gasoline bag can be folded into a small size, directly disposed into a steel gasoline tank and allowed to unfold. Expandable hoses are used to respectively connect to the existing gasoline inlet pipe, gasoline-measuring pipe and manhole of the steel gasoline tank. The soft properties of the soft gasoline bag are used to isolate the gasoline stored within the steel gasoline tank from the air, thereby reducing vaporization of gasoline, pollution and wastage.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: August 19, 2014
    Assignee: Full Most Co., Ltd.
    Inventors: Ming-Chun Weng, Ming-Tsang Yu, Wen-Pin Pen, Yu-Chi Li
  • Publication number: 20060157904
    Abstract: An apparatus for fixing a workpiece by a magnetic force includes a carrier and a fixing unit. The carrier is made of a magnetic material. The fixing unit is disposed on the workpiece, fixing the workpiece on the carrier. The fixing unit includes a supporting portion, a magnet and a connecting portion. The magnet is disposed in the supporting portion. The connecting portion is connected to the supporting portion and is used for being joined to the workpiece. The fixing unit is fixed on the carrier by a magnetic force, for fixing the workpiece on the carrier.
    Type: Application
    Filed: January 18, 2006
    Publication date: July 20, 2006
    Inventors: Yu-Chi Li, Kyi-Lyan Lee, Chun-Yi Cheng