Patents by Inventor Yu Chih Huang

Yu Chih Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200327214
    Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200294944
    Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.
    Type: Application
    Filed: May 31, 2020
    Publication date: September 17, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan TAI, Ting-Ting KUO, Yu-Chih HUANG, Chih-Wei LIN, Hsiu-Jen LIN, Chih-Hua CHEN, Ming-Da CHENG, Ching-Hua HSIEH, Hao-Yi TSAI, Chung-Shi LIU
  • Publication number: 20200294912
    Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20200279837
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10762319
    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng
  • Patent number: 10747119
    Abstract: A method of controlling a feedback system with a data matching module of an extreme ultraviolet (EUV) radiation source is disclosed. The method includes obtaining a slit integrated energy (SLIE) sensor data and diffractive optical elements (DOE) data. The method performs a data match, by the data matching module, of a time difference of the SLIE sensor data and the DOE data to identify a mismatched set of the SLIE sensor data and the DOE data. The method also determines whether the time difference of the SLIE sensor data and the DOE data of the mismatched set is within an acceptable range. Based on the determination, the method automatically validates a configurable data of the mismatched set such that the SLIE sensor data of the mismatched set is valid for a reflectivity calculation.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chih Huang, Chi Yang, Che-Chang Hsu, Li-Jui Chen, Po-Chung Cheng
  • Patent number: 10698994
    Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10672729
    Abstract: A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Ting-Ting Kuo, Yu-Chih Huang, Chih-Wei Lin, Hsiu-Jen Lin, Chih-Hua Chen, Ming-Da Cheng, Ching-Hua Hsieh, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 10658348
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10658334
    Abstract: Package structures and methods for forming the same are provided. The method includes providing a first integrated circuit die and forming a redistribution structure over the first integrated circuit die. The method also includes forming a base layer over the redistribution structure. The base layer has first and second openings. The first openings are wider than the second openings. The method further includes forming first bumps over the redistribution structure. The first bumps have a lower portion filling the first openings. In addition, the method includes bonding a second integrated circuit die to the redistribution structure through second bumps having a lower portion filling the second openings. There is a space between the second integrated circuit die and the base layer. The method also includes forming a molding compound layer over the base layer. The molding compound layer fills the space and surrounds the first and second bumps.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Cheng, Yu-Chih Huang, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai
  • Patent number: 10630455
    Abstract: A transmitting method of a transmitter for a non-orthogonal multiple access communication system, including: storing rules for calculating transmission rate combinations for simultaneously transmitting a first and a second application data; receiving a transmission grant for transmitting the first application data from a receiver; determining whether to transmit the second application data simultaneously; if yes, calculating multiple transmission rate combinations for simultaneously transmitting the first and the second application data based on the rules to calculate a transmission rate combination table, or generating the transmission rate combination table according to a pre-stored transmission rate combination table; selecting a transmission rate combination from the transmission rate combinations in the transmission rate combination table based on a transmission rate requirement of the second application data; and transmitting the first and the second application data simultaneously based on the selected
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 21, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Shin-Lin Shieh, Yu-Chih Huang
  • Publication number: 20200118900
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a conductive terminal. The RDL structure is disposed on and electrically connected to the die. The TIV is laterally aside the die and extends to contact a bottom surface and a sidewall of a redistribution layer of the RDL structure. The conductive terminal is electrically connected to the die through the RDL structure and the TIV.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Publication number: 20200105638
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Application
    Filed: February 4, 2019
    Publication date: April 2, 2020
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200103746
    Abstract: A method of controlling a feedback system with a data matching module of an extreme ultraviolet (EUV) radiation source is disclosed. The method includes obtaining a slit integrated energy (SLIE) sensor data and diffractive optical elements (DOE) data. The method performs a data match, by the data matching module, of a time difference of the SLIE sensor data and the DOE data to identify a mismatched set of the SLIE sensor data and the DOE data. The method also determines whether the time difference of the SLIE sensor data and the DOE data of the mismatched set is within an acceptable range. Based on the determination, the method automatically validates a configurable data of the mismatched set such that the SLIE sensor data of the mismatched set is valid for a reflectivity calculation.
    Type: Application
    Filed: September 11, 2019
    Publication date: April 2, 2020
    Inventors: Yu-Chih HUANG, Chi YANG, Che-Chang HSU, Li-Jui CHEN, Po-Chung CHENG
  • Publication number: 20200105730
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 2, 2020
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200105738
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 2, 2020
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Publication number: 20200058626
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Publication number: 20200059249
    Abstract: The disclosure provides a method and devices for transmitting information using polar code. In an exemplary embodiment in accordance with the disclosure, the disclosure is directed to a method of transmitting information using polar code. The method would include not limited to: generating a first data packet with a predetermined size and comprising data of multiple applications or multiple users; performing an interleaving operation which maps the first data packet based on a mapping algorithm to average the reliability of the data of multiple applications or multiple users; and generating a second data packet comprising interleaved first data packet.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 20, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Shin-Lin Shieh, Yu-Chih Huang
  • Patent number: 10510631
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a first connector. The RDL structure is connected to the die and includes a plurality of RDLs. The TIV is aside the die and penetrates through the RDL structure. The first connector is in electrical contact with the TIV and electrically connected to the die. The TIV is in electrical contact with the RDLs of the RDL structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Publication number: 20190340405
    Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: Chih-Hua Chen, Yu-Feng Chen, Chung-Shi Liu, Chen-Hua Yu, Hao-Yi Tsai, Yu-Chih Huang