Abstract: A semiconductor device includes a device layer, a semiconductor layer, a sensor element, a dielectric layer, a color filter layer, and a micro-lens. The semiconductor layer is over the device layer. The semiconductor layer has a plurality of microstructures thereon. Each of the microstructures has a substantially triangular cross-section. The sensor element is under the microstructures of the semiconductor layer and is configured to sense incident light. The dielectric layer is over the microstructures of the semiconductor layer. The color filter layer is over the dielectric layer. The micro-lens is over the color filter layer.

Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.

Abstract: A wafer transporting method includes following operations. A plurality of wafers are received in a semiconductor container attached to a mobile vehicle. An air processing system is coupled to a wall of the semiconductor container. The air processing system includes an inlet valve, an outlet valve, a pump between the inlet valve and the outlet valve, and a desiccant coupled to the pump. The semiconductor container is moved. The pump of the air processing system is turned on to extract air from inside the semiconductor container into the air processing system through the inlet valve. Humidity of the air is reduced when the air passes through the desiccant of the air processing system. The air is returned back to the semiconductor container through the outlet valve.

Abstract: A memory comprising a memory array, including a plurality of blocks, and control circuits comprising logic to execute operations is provided. The operations include decoding a read setup burst command identifying (i) an address of a first read setup block in a set of read setup blocks and (ii) a number of read setup blocks, as candidates for read setup operations. The operations further including, in response to the decoding of the read setup burst command, performing a read setup burst operation on a plurality of read setup blocks of the set of read setup blocks.

Abstract: A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.

Abstract: A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.

Abstract: A memory comprising a memory array, including a plurality of blocks, and control circuits comprising logic to execute operations is provided. The operations include decoding a read setup burst command identifying (i) an address of a first read setup block in a set of read setup blocks and (ii) a number of read setup blocks, as candidates for read setup operations. The operations further including, in response to the decoding of the read setup burst command, performing a read setup burst operation on a plurality of read setup blocks of the set of read setup blocks.

Abstract: A method of operating a memory is provided. The method includes, in response to an access of a block of memory updating a first queue to identify the accessed block in response to a determination that the block is not already identified in the first queue and a determination that the block is not already identified in a second queue, and updating the second queue to identify the accessed block of memory in response to a determination that the block is already identified in the first queue. The method further includes scanning the second queue to identify, as a read setup candidate, each block of the memory that is identified as present in the second queue longer than a threshold, and performing a read setup operation on a block of memory that has been identified as the read setup candidate.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.

Abstract: Novel processes for the preparation of a compound of Formula I-2 substantially free of the 5,6-trans isomer: wherein R2, R3 and R4 are as defined in the specification are provided. Novel intermediates for the preparations of isomer free Prostaglandins and derivatives thereof are also provided.