Patents by Inventor Yu-Chou Lee
Yu-Chou Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984516Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.Type: GrantFiled: February 16, 2023Date of Patent: May 14, 2024Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
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Patent number: 11967652Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.Type: GrantFiled: February 16, 2023Date of Patent: April 23, 2024Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
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Patent number: 11914429Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.Type: GrantFiled: March 9, 2023Date of Patent: February 27, 2024Assignee: Acer IncorporatedInventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee
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Patent number: 7855383Abstract: A semiconductor device and its manufacturing method are disclosed. The nitrogen flow is gradually changed to form a semiconductor device with a gate or a source/drain having a nitrified gradient layer structure. Different extents of nitrification inside the nitrified gradient layer structure provide protection and buffering to prevent the undercut after etching due to different materials in the multilayer structure or the interface effect.Type: GrantFiled: November 7, 2007Date of Patent: December 21, 2010Assignee: ChungHwa Picture Tubes, Ltd.Inventors: Ching-Yeh Kuo, Tsung-Chi Cheng, Yu-Chou Lee, Yea-Chung Shih, Wen-Kuang Tsao, Hsiang-Hsien Chung, Hung-Yi Hsu, Jui-Chung Chang
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Patent number: 7501652Abstract: A thin film transistor source/drain structure and the manufacturing method thereof are disclosed. The thin film transistor source/drain structure uses a sandwich structure to reduce the resistivity of the source/drain and upgrade the reliability. The sandwich structure preferably comprises a structure of AlNdN alloy/AlNd alloy/AlNdN alloy. The AlNdN alloy is used as a buffer layer or a diffusion barrier to prevent the AlNd alloy and an amorphous silicon layer from diffusing into each other. The other AlNdN alloy is used as a glue layer and to protect the AlNd alloy from being over-etched. The other AlNdN alloy can also prevent the AlNd alloy and the following formed ITO from contact and interaction.Type: GrantFiled: July 3, 2003Date of Patent: March 10, 2009Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Yu-Chou Lee, Tsung-Chi Cheng
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Publication number: 20080099853Abstract: A thin film transistor including a substrate, a first buffer layer, a gate, a gate insulation layer, a channel layer, a source and a drain is provided. The first buffer layer is disposed on the substrate and the first buffer is a silicide. The gate covers a portion of the first buffer layer, and the gate includes a first aluminum metal layer and a first protective layer disposed thereon. The gate insulation layer covers the gate, and the channel layer is disposed on part of the gate insulation layer. The source and the drain are disposed on the channel layer and separated form each other. Each of the source and the drain includes a second buffer layer, a second aluminum metal layer and a second protective layer. The second aluminum metal layer is disposed on the second buffer layer and the second protective layer is disposed thereon.Type: ApplicationFiled: April 14, 2007Publication date: May 1, 2008Applicant: CHUNGHWA PICTURE TUBES, LTD.Inventors: Chi-Jan Yang, Hsiy-Yu Chang, Yu-Chou Lee, Ying-Ming Wu
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Publication number: 20080061327Abstract: A semiconductor device and its manufacturing method are disclosed. The nitrogen flow is gradually changed to form a semiconductor device with a gate or a source/drain having a nitrified gradient layer structure. Different extents of nitrification inside the nitrified gradient layer structure provide protection and buffering to prevent the undercut after etching due to different materials in the multilayer structure or the interface effect.Type: ApplicationFiled: November 7, 2007Publication date: March 13, 2008Applicant: Chunghwa Picture Tubes., Ltd.Inventors: Ching-Yeh Kuo, Tsung-Chi Cheng, Yu-Chou Lee, Yea-Chung Shih, Wen-Kuang Tsao, Hsiang-Hsien Chung, Hung-Yi Hsu, Jui-Chung Chang
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Publication number: 20070187681Abstract: A thin film transistor and method of fabrication a thin film transistor and a pixel structure are provided. First, a gate is formed on the substrate. Then, a gate-isolating layer is formed on the substrate to cover the gate electrode. After that, a source/drain is formed on the gate-isolating layer and exposes a portion of the gate-isolating layer above the gate electrode. Then, a channel is formed on the portion of the gate-isolating layer above the gate. The source/drain layer is formed before forming the channel to prevent the channel from over etching as forming the source/drain layer. Therefore, the yields of manufacturing thin film transistor and pixel structure can be improved.Type: ApplicationFiled: April 26, 2007Publication date: August 16, 2007Applicant: CHUNGHWA PICTURE TUBES, LTD.Inventors: Chiun-Hung Chen, Yu-Chou Lee
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Publication number: 20060238647Abstract: A video data accessing method and device which perform loading actions and saving actions respectively in two stages, wherein the loading or saving actions depend on whether the received video signal contains valid data. When the received data is valid, only the saving action is performed to a register at each clock cycle, at the same time the register will not be read.Type: ApplicationFiled: April 26, 2005Publication date: October 26, 2006Applicant: VIHONOR OPTO-ELECTRONICS CO., LTD.Inventor: Yu-Chou Lee
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Publication number: 20060199314Abstract: A thin film transistor and method of fabrication a thin film transistor and a pixel structure are provided. First, a gate is formed on the substrate. Then, a gate-isolating layer is formed on the substrate to cover the gate electrode. After that, a source/drain is formed on the gate-isolating layer and exposes a portion of the gate-isolating layer above the gate electrode. Then, a channel is formed on the portion of the gate-isolating layer above the gate. The source/drain layer is formed before forming the channel to prevent the channel from over etching as forming the source/drain layer. Therefore, the yields of manufacturing thin film transistor and pixel structure can be improved.Type: ApplicationFiled: March 2, 2005Publication date: September 7, 2006Inventors: Chiun-Hung Chen, Yu-Chou Lee
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Publication number: 20060197089Abstract: A semiconductor device and its manufacturing method are disclosed. The nitrogen flow is gradually changed to form a semiconductor device with a gate or a source/drain having a nitrified gradient layer structure. Different extents of nitrification inside the nitrified gradient layer structure provide protection and buffering to prevent the undercut after etching due to different materials in the multilayer structure or the interface effect.Type: ApplicationFiled: March 3, 2005Publication date: September 7, 2006Applicant: Chunghwa Picture Tubes., Ltd.Inventors: Ching-Yeh Kuo, Tsung-Chi Cheng, Yu-Chou Lee, Yea-Chung Shih, Wen-Kuang Tsao, Hsiang-Hsien Chung, Hung-Yi Hsu, Jui-Chung Chang
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Publication number: 20060144696Abstract: A magnetron sputtering process is provided. First, a reaction chamber including a substrate base, a target comprised of Al or its alloy or other metals or their alloy with higher melting point, and a magnetron device. Next, a substrate is disposed onto the substrate base. The pressure within the reaction chamber is set from 0.1 pa˜0.35 pa, and then a sputtering process is initiated within the reaction chamber to deposit a film on the substrate. Because the pressure within the reaction chamber is set from 0.1 pa˜0.35 pa, a better step coverage can be achieved during the sputtering process so that a continuous film can be deposited on the substrate without the broken or defective climbing portion of the film. Therefore, the yield of film deposition on the substrate can also be significantly increased.Type: ApplicationFiled: May 6, 2005Publication date: July 6, 2006Inventors: Yu-Chou Lee, Hsiang-Hsien Chung, Hung-I Hsu
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Publication number: 20060144695Abstract: A sputtering process of indium tin oxide (ITO) is provided. The sputtering process includes the following steps. First, a substrate is moved into a reaction chamber, wherein an ITO target is disposed inside the reaction chamber. Then, a plasma gas and a reaction gas are provided into the reaction chamber to form an ITO layer on the substrate. The reaction gas comprises at least hydrogen having a volume ratio of 1%˜4% based on the total gas volume in the reaction chamber. Furthermore, a method of forming an indium tin oxide layer is also provided.Type: ApplicationFiled: March 24, 2005Publication date: July 6, 2006Inventors: Yu-Chou Lee, Tsung-Chi Cheng, Hung-I Hsu
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Patent number: 6977193Abstract: A Thin Film Transistor (TFT) manufacture method, comprising manufacture of a gate, a gate isolation layer, a channel layer, and a source/drain. Wherein, the manufacture of the channel layer comprises: forming a first a-Si layer by using a low deposition rate (LDR) (Chemical Vapor Deposition, CVD); forming a second a-Si layer by using a high deposition rate (HDR); and forming an N+Mixed a-Si layer. When the first a-Si layer is formed in the present invention, the flux ratio of H2/SiH4 is adjusted to a range from 0.40 to 1.00 to increase the number of defects in the first a-Si layer. When the TFT is irradiated by the light, the photo leakage current generated in the channel layer is trapped in the defects in the first a-Si layer. Therefore, the TFT photo leakage current can be significantly reduced.Type: GrantFiled: March 12, 2004Date of Patent: December 20, 2005Assignee: Chunghwa Picture TubesInventors: Yu-Chou Lee, Yi-Tsai Hsu
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Publication number: 20050164592Abstract: In those conventional arts, for large-size LCD, the process of copper damascene interconnect has some problems of forming a uneven copper seed layer and forming hollows during electrical plating due to the electrical plating area being too large to electroplate uniformly. In this invention, it employs a Cu tape to directly stick on a substrate to replace forming a copper seed layer and electroplating. Hence, the invention avoids the problem of unevenness and hollows in those conventional arts and so the Cu lines can be applied to the large-size LCD.Type: ApplicationFiled: March 21, 2005Publication date: July 28, 2005Applicant: Chungwha Picture Tubes, Ltd.Inventor: Yu-Chou Lee
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Patent number: 6921698Abstract: A method for fabricating a thin film transistor (TFT) is described. A MoNb gate is formed on a substrate, and an insulating layer is formed on the substrate covering the gate. A channel layer is formed on the insulating layer above the gate, and a source/drain is formed on the channel layer to constitute a TFT. Since the gate is constituted of a MoNb layer, the contact resistance thereof can be reduced.Type: GrantFiled: September 29, 2003Date of Patent: July 26, 2005Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Yu-Chou Lee, Wen-Kuang Tsao
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Publication number: 20050006645Abstract: A method for fabricating a thin film transistor (TFT) is described. A MoNb gate is formed on a substrate, and an insulating layer is formed on the substrate covering the gate. A channel layer is formed on the insulating layer above the gate, and a source/drain is formed on the channel layer to constitute a TFT. Since the gate is constituted of a MoNb layer, the contact resistance thereof can be reduced.Type: ApplicationFiled: September 29, 2003Publication date: January 13, 2005Inventors: Yu-Chou Lee, Wen-Kuang Tsao
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Patent number: 6841431Abstract: A method for reducing the contact resistance using plasma process tries to solve the problem that the cleaning process could not remove both the residues and oxides on the etched surface effectively. A plasma treating process is performed after the cleaning process and before any following process. Herein, the plasma treating process uses the plasma(s) to physically and/or chemically react with the etched surface. For example, inert gas plasma is used to remove these residues and the oxides, and then hydrogen plasma is used to compensate the unsaturated bonds by inducing the ions bombardment of the inert gas plasma.Type: GrantFiled: January 29, 2003Date of Patent: January 11, 2005Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Yu-Chou Lee, Min-Ching Hsu
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Publication number: 20050001438Abstract: A robotic arm that has a main body and pads thereon can prevent electrostatic damage. These pads are used to carry substrates between and in processing machines. A material of these pads is the same as or similar to the material of the substrate to lower the amount of the electrostatic charges produced during the manufacturing process. Therefore, the electrostatic charges cannot damage the electronic devices on the substrate.Type: ApplicationFiled: February 5, 2004Publication date: January 6, 2005Inventors: Yu-Chou Lee, Ying-Ming Wu, Chien-Yu Chen
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Publication number: 20040201838Abstract: A defect identifying apparatus marks a defect location, obviating manual marking in the LCD manufacturing process. The defect identifying apparatus includes a microscope and a defect marker. The defect marker is fastened to a base of the microscope. The defect marker includes an ink jet and a support frame. The support frame is employed to fix the ink jet to the base of the microscope. The ink jet should be positioned between an objective lens and its focal plane so as to avoid scratching the LCD substrate.Type: ApplicationFiled: August 20, 2003Publication date: October 14, 2004Inventors: Yu-Chou Lee, Ting-Hui Lee, Chen-Hsien Wang