Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: The present invention provides a method for preventing and/or treating a NSAID-induced gastric ulcer. The method comprises administrating an effective amount of a lactic acid bacterium set to a subject. The lactic acid bacterium set comprises Lactobacillus plantarum GKD7 and Pediococcus acidilactici GKA4.

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

Abstract: A pixel unit. A first thin film transistor comprises a first control terminal receiving a scan signal, a first electrode receiving a data signal, and a second electrode. A second thin film transistor comprises a second control terminal coupled to the second electrode, a third electrode receiving a first voltage, a fourth electrode, and a fifth electrode coupled to one of the third and the fourth electrodes. A capacitor is coupled between the second control terminal and the third electrode. A light-emitting device is coupled between the fourth electrode and a second voltage.

Abstract: Embodiments of a system for displaying images include a light emitting device with a plurality of photo sensors. Each photo sensor includes a PIN diode composed of an N+ doped semiconductor region, a P+ doped semiconductor region, and an intrinsic semiconductor region formed therebetween. An insulated control gate overlaps the intrinsic semiconductor region and is operative to provide the PIN diode with a controllable electric characteristic with respect to a saturation photo current at a saturation voltage.

Abstract: A pixel unit. A first thin film transistor comprises a first control terminal receiving a scan signal, a first electrode receiving a data signal, and a second electrode. A second thin film transistor comprises a second control terminal coupled to the second electrode, a third electrode receiving a first voltage, a fourth electrode, and a fifth electrode coupled to one of the third and the fourth electrodes. A capacitor is coupled between the second control terminal and the third electrode. A light-emitting device is coupled between the fourth electrode and a second voltage.