Patents by Inventor Yu Chung

Yu Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240185934
    Abstract: A request to perform a program operation to program a set of memory cells on a memory device comprising a sense amplifier circuit is received. A defect indicator associated with the set of memory cells is determined to satisfy a defect condition. A modified sensing time period, exceeding a default sensing time period, is determined based on the defect indicator. The program operation is performed using the modified sensing time period during a program verify phase of the program operation.
    Type: Application
    Filed: November 28, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Chung Lien, Zhenming Zhou
  • Publication number: 20240185935
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells in the block using a first bitline voltage applied during a program verify phase, wherein the first bitline voltage is higher than a default program verify bitline voltage.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Chung Lien, Zhenming Zhou
  • Publication number: 20240184449
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.
    Type: Application
    Filed: January 9, 2023
    Publication date: June 6, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
  • Publication number: 20240185924
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells associated with a wordline in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells associated with the wordline in the block using a first pass voltage applied during a program verify phase, wherein the first pass voltage is lower than a default program verify pass voltage.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Chung Lien, Zhenming Zhou
  • Publication number: 20240185931
    Abstract: A request to perform a program operation to program a set of memory cells on a memory device is received. A defect indicator associated with the set of memory cells is determined to satisfy a defect condition. A value of a program verify parameter is determined based on the defect indicator. The program operation is performed using the value of the program verify parameter during a program verify phase of the program operation.
    Type: Application
    Filed: November 28, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Chung Lien, Jun Wan, Zhenming Zhou
  • Publication number: 20240177781
    Abstract: A method for partial block read compensation can include receiving a read request that specifies a memory cell connected to a string of series-connected memory cells in an array of memory cells on a memory device, the string located at an intersection of a wordline and a bitline, and causing a first voltage applied to the wordline to which the specified memory cell is connected to ramp to a first predetermined value. The method can include causing a second voltage applied to the bitline to which the specified memory cell is connected to ramp to a second predetermined value, and can include comparing, using a current comparator, a current along the string with a reference current to generate an analog output signal. It can also include causing a voltage offset, based on the analog output signal, to be applied to a read voltage level during a sensing operation.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 30, 2024
    Inventors: Yu-Chung Lien, Jun Wan, Zhenming Zhou
  • Publication number: 20240173034
    Abstract: Systems, apparatuses, and methods disclosed herein may be directed to clips for medical implementation, including clips for a portion of a heart. The clips may be configured to close the portion of the heart, to reduce blood flow therethrough as well as passage of clots or other undesired materials. In examples, the clips may be configured to close the left atrial appendage (LAA). The closure of the LAA may reduce the possibility of stroke or other maladies stemming from fluid flow with the LAA. In examples, the clips may be positioned exterior of the LAA, to extend over an outer surface of the LAA for closure.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 30, 2024
    Inventors: Harvey H. Chen, Manouchehr A. Miraki, Rodolfo Rodriguez, Erin E. Castioni, Maria L. Saravia, Stephen Epstein, Luke Anthony Zanetti, Ashley Nicolette Hinga (formerly Keffer), Stephen Cournane, Felino V. Cortez, JR., Nancy Ling Chung, Daniel Yasevac, Andrew Ryan, Slava Arabagi, Jaime L. Baluyot, Sooji Van Echten, Da-Yu Chang, John Richard Carpenter, Sai Prasad Uppalapati, Pui Tong Ho, Jason Thai Le, Adam J. Yestrepsky
  • Publication number: 20240176508
    Abstract: A system with a memory device and a processing device operatively coupled with the memory device, to perform operations including identifying a lifecycle state associated with a segment of the memory device, selecting, based on the lifecycle state, an erase policy for performing an erase operation with respect to the segment, and causing the erase operation to be performed with respect to the segment in accordance with the erase policy.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Inventors: Yu-Chung Lien, Zhongguang Xu, Ronit Roneel Prakash, Zhenming Zhou
  • Publication number: 20240178631
    Abstract: A laser diode includes an original substrate having a substrate coefficient of thermal expansion, an epitaxy structure formed on the original substrate, and a composite multi-layer metal board disposed below the original substrate and at least including a first metal layer and a second metal layer. The first metal layer and the second metal layer are stacked, a material of the first metal layer is different from a material of the second metal layer, and the composite multi-layer metal board has a modified coefficient of thermal expansion. The original substrate has an initial thickness as the epitaxy structure is grown thereon, the original substrate is thinned to a combining thickness for attaching the composite multi-layer metal board, and the modified coefficient of thermal expansion of the composite multi-layer metal board is proximate to the substrate coefficient of thermal expansion.
    Type: Application
    Filed: May 26, 2023
    Publication date: May 30, 2024
    Inventors: Ai-Sen LIU, Hsiang-An FENG, Cheng-Yu CHUNG, Ya-Li CHEN
  • Publication number: 20240173795
    Abstract: A cavity forming method includes the steps of: providing the material modification processing device; according to the cavity topography of the workpiece, utilizing the material modification processing device to perform local modification including: calculating the laser-light shaping and scanning information, and based on the laser-light shaping and scanning information to have the optical axis adjustment unit to adjust positions of the laser-light shaping and scanning processing module and the processing stage, such that the area of the workpiece to be projected by the Bessel beam can be formed as the modified area; and, etching the modified area to form a cavity of the cavity topography. In additional, a material modification processing device is also provided.
    Type: Application
    Filed: December 21, 2022
    Publication date: May 30, 2024
    Inventors: FU-LUNG CHOU, Chien-Jung Huang, Yu-Chung Lin
  • Patent number: 11995246
    Abstract: A method for touchless gesture recognition is provided. The method includes transmitting ultrasonic signals via a speaker. The method includes generating ultrasonic signals. The method includes receiving the reflected ultrasonic signals from an object via two or more microphones. The method includes computing a frequency shift according to the reflected ultrasonic signals. The method includes identifying a gesture that corresponds to a movement of the object according to the frequency shift. The method includes performing a function that corresponds to the gesture.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: May 28, 2024
    Assignee: FORTEMEDIA, INC.
    Inventors: Yu-Xuan Xu, Ching-Lung Chan, Shih-Chung Wang, Yen-Son Paul Huang, Shih-Chin Gong
  • Publication number: 20240170071
    Abstract: A processing device is operatively coupled to an array of memory cells. The processing device determines that a media endurance metric value for a string of the array of memory cells satisfies a first threshold criterion based on a first threshold value. The processing device further controls, based on the media endurance metric value, a ramp rate of a program pulse applied to a wordline of the string.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 23, 2024
    Inventors: Yu-Chung Lien, Joshua Garrison, Zhenming Zhou
  • Publication number: 20240170553
    Abstract: A semiconductor device according to the present disclosure includes a stack of first channel layers, first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, a stack of second channel layers stacked over the first channel layers, third and fourth S/D epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, and a dielectric isolation layer disposed under the first and second S/D epitaxial features. A total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers. The dielectric isolation layer is in physical contact with at least a bottommost one of the first channel layers.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 23, 2024
    Inventors: Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng
  • Publication number: 20240170526
    Abstract: A back side illumination (BSI) image sensor includes an epitaxial substrate, a deep trench isolation (DTI) structure from one surface to the other surface of the epitaxial substrate, a buried oxide layer on the epitaxial substrate, an epitaxial layer, a well region, a floating diffusion (FD) region, a shallow trench isolation (STI) structure, and vertical transfer gates (VTGs). The buried oxide layer has openings exposing the epitaxial substrate, and the epitaxial layer is formed on the epitaxial substrate and covers the buried oxide layer. The well region is in the epitaxial layer and the epitaxial substrate. The FD region is in the well region above the buried oxide layer, and a width of the buried oxide layer is larger than that of the FD region. The STI structure is in the epitaxial layer. The VTGs are in the epitaxial layer and through the openings of the buried oxide layer.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 23, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih-Ping Chung, Saysamone Pittikoun, Chih-Hao Peng, Ming-Yu Ho
  • Patent number: 11988831
    Abstract: A method of displaying a rear-view image and a mobile device using the method are provided. The method includes: receiving the rear-view image; displaying a virtual dashboard through a display; and displaying the rear-view image on a default area of the virtual dashboard in response to receiving a signal associated with a direction indicator light, wherein the default area corresponds to the direction indicator light.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 21, 2024
    Assignee: Kinpo Electronics, Inc.
    Inventors: Yu Chi Chen, Hsien Chung Chen, Sheng-Chang Wu
  • Publication number: 20240153901
    Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 9, 2024
    Inventors: Yu-Hung Lin, Han-Jong Chia, Wei-Ming Wang, Kuo-Chung Yee, Chen Chen, Shih-Peng Tai
  • Publication number: 20240140029
    Abstract: The present application relates to an apparatus and method for three-dimensional printing. The apparatus comprises a gantry, a tilting print head and a rotary table. The tilting print head comprises an extruder, an elongated nozzle connected to the extruder and a filament tube connected to side-entrance of the extruder. The extruder is configured to rotate around the tilting axis. The filament tube is configured to feed the printing material into the extruder. The tilting print head is configured to control the printing material to enter the extruder through the filament tube, spiral through the extruder and enter the elongated nozzle. As the entrance is arranged on the side of the extruder and the filament tube is close to the tilting axis, the printing material can be more stable when the tilting print head rotates upward or downward.
    Type: Application
    Filed: June 30, 2023
    Publication date: May 2, 2024
    Inventors: Man Fai CHUNG, Tak Yu LAU
  • Publication number: 20240147405
    Abstract: A controlling method for a wireless communication device is provided. The controlling method for the wireless communication device includes: attaching a first Universal Subscriber Identity Module (USIM) to a Long-Term Evolution (LTE) network; determining whether a second USIM is camped on the LTE network; detecting whether a paging collision is happened, if the second USIM is camped on the LTE network; generating a requested International Mobile Subscriber Identity (IMSI) offset for the second USIM, if the paging collision is happened, wherein the requested IMSI offset is 1 or min(T, nB)?1, T is a default paging period and nB is a number of paging occurrences within the default paging period; transmitting an attach request with the requested IMSI offset to the LTE network for the second USIM; receiving a negotiated IMSI offset from the LTE network; and attaching the second USIM to the LTE network with the negotiated IMSI offset.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Yu LIN, Ya-ling Hsu, Wan-Ting Huang, Yi-Han CHUNG, Yi-Cheng CHEN
  • Publication number: 20240145378
    Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ting Liu, Chen-Chiu Huang, Dian-Hau Chen, Hung-Chao Kao, Hsiang-Ku Shen, Wen-Chiung Tu, Li Chung Yu, Yu-Chung Lai
  • Patent number: D1028971
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 28, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hsing-Yi Kao, Ming-Chung Liu, Yu-Hsin Chen