Abstract: A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.

Abstract: A method and a system for predicting shrinkable yield for business assessment of integrated circuit design shrink are provided. An assessment system is provided to determine cost benefits of a design shrink of an integrated circuit chip. A cost benefit analysis across different design shrink technologies is provided early in the process, so that business decisions regarding employment of design shrinks can be made as early as possible.

Abstract: A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.

Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Abstract: Aspects of the present invention provide a method and a system for predicting shrinkable yield for business assessment of integrated circuit design shrink. An assessment system is provided to determine cost benefits of a design shrink of an integrated circuit chip. A cost benefit analysis across different design shrink technologies is provided early in the process, so that business decisions regarding employment of design shrinks can be made as early as possible.

Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Abstract: Described is a semiconductor device structure with improved iso-dense bias and methods of producing thereof. Non-functional patterns may be added to an integrated circuit layout design. These patterns may be located next to an isolated transistor or an array of densely-packed transistors in order to mitigate the iso-dense bias effects. Furthermore, the patterns can take on a variety of geometric shapes and sizes.

Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Abstract: The present invention provides a method for cleaning wafer surfaces in a scrubber by ion doped deionized water without the electrostatic discharge problem. The method can be carried out by first doping a quantity of deionized water with at least one species of ions from the group consisting of OH−, F−, Cl−, NH4+ and H+ any other suitable ions. The added ions significantly reduce the resistivity of the DI water such that DI water is no longer a perfect insulator and therefore, when sprayed onto wafer surfaces covered by an insulating material, the generation of electrostatic charges is significantly reduced. As a result, the undesirable effect of electrostatic discharge can be significantly reduced or eliminated and the yield of the wafer fabrication process can be improved.