Patents by Inventor Yu-Fang Tsai
Yu-Fang Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113221Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.Type: ApplicationFiled: November 28, 2023Publication date: April 4, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsiung TSAI, Shahaji B. MORE, Cheng-Yi PENG, Yu-Ming LIN, Kuo-Feng YU, Ziwei FANG
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Publication number: 20220238502Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.Type: ApplicationFiled: April 12, 2022Publication date: July 28, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tsung-Yueh TSAI, Meng-Jen WANG, Yu-Fang TSAI, Meng-Jung CHUANG
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Patent number: 11302682Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.Type: GrantFiled: October 25, 2019Date of Patent: April 12, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tsung-Yueh Tsai, Meng-Jen Wang, Yu-Fang Tsai, Meng-Jung Chuang
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Patent number: 11042630Abstract: A method for determining which web page among multiple candidate web pages is similar to a given web page. For each candidate web page, a set of scoring rules is provided to score the components therein. When the given web page is compared against a candidate web page, each component that is found in both the given web page and the candidate web page under examination is given a score in accordance with the set of scoring rules that is specific to that web page under examination. A composite similarity score is computed for each comparison between the given webpage and a candidate web page. If the composite similarity score exceeds a predefined threshold value for a comparison between the given webpage and a candidate web page, that candidate web page is deemed the web page that is similar.Type: GrantFiled: August 22, 2019Date of Patent: June 22, 2021Assignee: Trend Micro IncorporatedInventors: Chao-Yu Chen, Peng-Shih Pu, Yu-Fang Tsai
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Publication number: 20210125974Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.Type: ApplicationFiled: October 25, 2019Publication date: April 29, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tsung-Yueh TSAI, Meng-Jen WANG, Yu-Fang TSAI, Meng-Jung CHUANG
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Publication number: 20200042696Abstract: A method for determining which web page among multiple candidate web pages is similar to a given web page. For each candidate web page, a set of scoring rules is provided to score the components therein. When the given web page is compared against a candidate web page, each component that is found in both the given web page and the candidate web page under examination is given a score in accordance with the set of scoring rules that is specific to that web page under examination. A composite similarity score is computed for each comparison between the given webpage and a candidate web page. If the composite similarity score exceeds a predefined threshold value for a comparison between the given webpage and a candidate web page, that candidate web page is deemed the web page that is similar.Type: ApplicationFiled: August 22, 2019Publication date: February 6, 2020Applicant: Trend Micro IncorporatedInventors: Chao-Yu CHEN, Peng-Shih PU, Yu-Fang TSAI
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Patent number: 9059379Abstract: Light-emitting semiconductor packages and related methods. The light-emitting semiconductor package includes a central barrier, a plurality of leads, a light-emitting device, a first encapsulant, a package body, and a second encapsulant. The light-emitting device is disposed in the interior space defined by the central barrier and is electrically connected to the leads surrounding the central barrier. The light-emitting device includes upper and lower light-emitting surfaces. The first encapsulant and the second encapsulant cover the upper and lower light-emitting surfaces, respectively. The package body encapsulates portions of the central barrier, portions of each of the leads, and the first encapsulant. The light-emitting semiconductor package can emit light from both the upper and lower sides thereof.Type: GrantFiled: October 29, 2012Date of Patent: June 16, 2015Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yen-Ting Kuo, Ping-Cheng Hu, Yu-Fang Tsai
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Patent number: 8994156Abstract: Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.Type: GrantFiled: July 29, 2013Date of Patent: March 31, 2015Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Po-Shing Chiang, Ping-Cheng Hu, Yu-Fang Tsai
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Publication number: 20140117388Abstract: Light-emitting semiconductor packages and related methods. The light-emitting semiconductor package includes a central barrier, a plurality of leads, a light-emitting device, a first encapsulant, a package body, and a second encapsulant. The light-emitting device is disposed in the interior space defined by the central barrier and is electrically connected to the leads surrounding the central barrier. The light-emitting device includes upper and lower light-emitting surfaces. The first encapsulant and the second encapsulant cover the upper and lower light-emitting surfaces, respectively. The package body encapsulates portions of the central barrier, portions of each of the leads, and the first encapsulant. The light-emitting semiconductor package can emit light from both the upper and lower sides thereof.Type: ApplicationFiled: October 29, 2012Publication date: May 1, 2014Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yen-Ting Kuo, Ping-Cheng Hu, Yu-Fang Tsai
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Patent number: 8674487Abstract: A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface.Type: GrantFiled: March 15, 2012Date of Patent: March 18, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Lin-Wang Yu, Ping-Cheng Hu, Che-Chin Chang, Yu-Fang Tsai
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Publication number: 20130307157Abstract: Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.Type: ApplicationFiled: July 29, 2013Publication date: November 21, 2013Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Po-Shing Chiang, Ping-Cheng Hu, Yu-Fang Tsai
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Publication number: 20130241041Abstract: A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface.Type: ApplicationFiled: March 15, 2012Publication date: September 19, 2013Inventors: Lin-Wang Yu, Ping-Cheng Hu, Che-Chin Chang, Yu-Fang Tsai
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Patent number: 8502363Abstract: A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.Type: GrantFiled: March 28, 2012Date of Patent: August 6, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Po-Shing Chiang, Ping-Cheng Hu, Yu-Fang Tsai
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Publication number: 20130009313Abstract: A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.Type: ApplicationFiled: March 28, 2012Publication date: January 10, 2013Inventors: Po-Shing Chiang, Ping-Cheng Hu, Yu-Fang Tsai
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Publication number: 20070290318Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. -The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.Type: ApplicationFiled: August 27, 2007Publication date: December 20, 2007Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Su TAO, Yu-Fang TSAI
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Patent number: 7291926Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.Type: GrantFiled: February 14, 2006Date of Patent: November 6, 2007Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Su Tao, Yu-Fang Tsai
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Patent number: 7253529Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.Type: GrantFiled: December 31, 2004Date of Patent: August 7, 2007Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Su Tao, Yu-Fang Tsai
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Patent number: 7129583Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.Type: GrantFiled: December 31, 2004Date of Patent: October 31, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Su Tao, Yu-Fang Tsai
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Publication number: 20060138631Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.Type: ApplicationFiled: February 14, 2006Publication date: June 29, 2006Inventors: Su Tao, Yu-Fang Tsai
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Publication number: 20060131718Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.Type: ApplicationFiled: February 14, 2006Publication date: June 22, 2006Inventors: Su Tao, Yu-Fang Tsai