Abstract: A display device includes a pixel array substrate and a circuit board. The pixel array substrate has a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface and the second surface. Multiple bonding pads are located on the first surface. The circuit board is bent from above the first surface of the pixel array substrate to below the second surface. The circuit board is electrically connected to the bonding pads and includes a thermoplastic substrate. The thermoplastic substrate includes a third surface facing the pixel array substrate and a fourth surface opposite to the third surface. The thermoplastic substrate includes a first bend formed by thermoplastics.

Abstract: A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer. The first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates through a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first cell unit and a second cell unit. The first cell unit and the second cell unit include a first shared bottom electrode, and the first insulating structure is disposed directly on the first shared bottom electrode.

Abstract: A ReRAM device includes an interlayer dielectric (ILD), a lower conductive plug, a resistance-switching element (RSE) and an upper conductive plug. The ILD has an upper surface. The lower conductive plug is disposed in the ILD, and has a top surface lower than the upper surface. The RSE is disposed above the top surface and electrically contacts with the top surface. The upper conductive plug is disposed above the RSE and electrically contacts with the RSE.

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first electrode, a second electrode on one side of the first electrode, and a resistive switching film between the first electrode and the second electrode. The first electrode, the resistive switching film and the second electrode are arranged along the first direction. The second semiconductor structure includes a first via and a first metal layer on the first via along a second direction and electrically connected to the first via. The first direction is perpendicular to the second direction. An upper surface of the first electrode, an upper surface of the second electrode, an upper surface of the resistive switching film and an upper surface of the first metal layer are coplanar.

Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

Abstract: A resistive memory device includes a dielectric layer, a via connection structure, a stacked structure, and an insulating structure. The via connection structure is disposed in the dielectric layer. The stacked structure is disposed on the via connection structure and the dielectric layer. The insulating structure penetrates through the stacked structure in a vertical direction and divides the stacked structure into a first memory cell unit and a second memory cell unit. The first memory cell unit includes a first bottom electrode, and the second memory cell unit includes a second bottom electrode separated from the first bottom electrode by the insulating structure. The via connection structure is electrically connected with the first bottom electrode and the second bottom electrode.

Abstract: A data error-detecting method for detecting errors before C1 decoding procedure is provided. First, a bit modulation is performed for modulating data channel bits obtained from an optical disk into 8-bit data. When the data channel bits is determined to introduce a legal mapping, an erasure bit having a first value is derived and tagged at the modulated 8-bit data, otherwise an erasure bit having a second value is derived and tagged at the modulated 8-bit data. After the 8-bit data being arranged as a codeword composed of 32 erasure bits respectively tagged with 32 8-bit data, counting the number of the modulated 8-bit data tagged with the erasure bit having the second value. When the counted number is less than 4, the codeword composed modulated 8-bits data tagged with the erasure bits having the second value can be corrected.

Abstract: A USB control circuit for saving power and the method thereof employs a first logic circuit to generate a control signal that turns on the power of a transmitting module, so as to enable the transmitting module just before sending data. The above-mentioned USB control circuit and the method thereof also employs a second logic circuit to select the control signal, so as to solve the problem in USB handshaking processes and to provide a selection for changing the control signal.

Abstract: A USB control circuit for saving power and the method thereof employs a first logic circuit to generate a control signal that turns on the power of a transmitting module, so as to enable the transmitting module just before sending data. The above-mentioned USB control circuit and the method thereof also employs a second logic circuit to select the control signal, so as to solve the problem in USB handshaking processes and to provide a selection for changing the control signal.