Patents by Inventor Yu Han

Yu Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240126356
    Abstract: The present application discloses a power supply redundancy control system for a GPU server, comprising a power supply redundancy module, a BMC, a CPLD and a GPU module. The power supply redundancy module comprises a first PSU and a second PSU, and the GPU module comprises several GPUs, the first PSU is connected to the CPLD by means of a first bus. The second PSU is connected to the CPLD by means of a second bus. The BMC is connected to the CPLD by means of a first I2C bus and a second I2C bus, and sends heartbeat information to the CPLD. The CPLD is connected to the BMC by means of a third bus and a fourth bus, and the CPLD is connected to the several GPUs by means of a third I2C bus. In the present application, when the BMC is abnormalous or restarted, the CPLD can control the overall power consumption of the server, and can also ensure that the server will not go down, reducing the loss brought to a user due to the BMC being abnormalous or restarted.
    Type: Application
    Filed: January 28, 2022
    Publication date: April 18, 2024
    Inventors: Yue ZHANG, Hongrui HAN, Suhua WANG, Yu LIU
  • Publication number: 20240128149
    Abstract: Some implementations described herein include systems and techniques for fabricating a semiconductor die package that includes a cooling interface region formed in surface of an integrated circuit die. The cooling interface region, which includes a combination of channel regions and pillar structures, may be directly exposed to a fluid above and/or around the semiconductor die package.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 18, 2024
    Inventors: Cheng-Chieh HSIEH, Wei-Kong SHENG, Ke-Han SHEN, Yu-Jen LIEN
  • Publication number: 20240125916
    Abstract: An indoor positioning method includes scanning for registered Wi-Fi nodes with known coordinates to generate a list of the registered Wi-Fi nodes. The method also includes performing a ranging operation by (i) selecting nodes to range with from the list of the registered Wi-Fi nodes, and (ii) processing ranging responses from the selected nodes to generate a series of distance measurements. The method further includes obtaining a series of sensor readings generated by one or more inertial measurement units (IMUs) of a device. The method also includes estimating a position of the device based on the series of distance measurements and the series of sensor readings using first and second filtering operations that are performed in parallel.
    Type: Application
    Filed: June 27, 2023
    Publication date: April 18, 2024
    Inventors: Rebal Al Jurdi, Hao Chen, Jianyuan Yu, Boon Loong Ng, Kyu-Hui Han, Jianzhong Zhang
  • Patent number: 11961681
    Abstract: A multilayer capacitor includes a capacitor body including dielectric layers and internal electrodes alternately disposed with the dielectric layers interposed therebetween; and an external electrode disposed on the capacitor body to be connected to one or more of the internal electrodes. Porosity of ends of the internal electrodes is less than 50% on an interfacial surface between a margin of the capacitor body in a width direction the capacitor body and the internal electrodes.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yu Kwang Seo, Berm Ha Cha, Kang Hyun Lee, Jong Hwa Lee, Jong Han Kim
  • Patent number: 11963429
    Abstract: A display module (10) includes: a display panel (12) and a circuit board (14) coupled to the display panel (12). The display panel (12) includes a driving chip (122) and a display unit (124); and the circuit board (14) includes a first filter element (142), wherein the first filter element (142) is coupled to the driving chip (122) and the display unit (124), and a direct current signal output by the driving chip (122) is filtered by the first filter element (142) and then transmitted to the display unit (124). The present disclosure also provides a display apparatus (100).
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: April 16, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yu Wang, Yi Zhang, Tingliang Liu, Tinghua Shang, Huijuan Yang, Yang Zhou, Pengfei Yu, Linhong Han, Hao Zhang, Xiaofeng Jiang, Huijun Li
  • Patent number: 11961444
    Abstract: The disclosure provides a transparent display device including a display panel. The display panel includes a display area, a non-display area, and a plurality of pixels. The non-display area is adjacent to the display area. The plurality of pixels are disposed in the display area. A difference between a transmittance of the display area and a transmittance of the non-display area is less than 30% of the transmittance of the display area.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: April 16, 2024
    Assignee: Innolux Corporation
    Inventors: Yu-Chia Huang, Yuan-Lin Wu, Tsung-Han Tsai, Kuan-Feng Lee
  • Patent number: 11955446
    Abstract: The present disclosure relates to a method for forming a semiconductor device structure. The method includes forming a first semiconductor die and forming a second semiconductor die. The first semiconductor die includes a first metal layer, a first conductive via over the first metal layer, and a first conductive polymer liner surrounding the first conductive via. The second semiconductor die includes a second metal layer, a second conductive via over the second metal layer, and a second conductive polymer liner surrounding the second conductive via. The method also includes forming a conductive structure electrically connecting the first metal layer and the second metal layer by bonding the second semiconductor die to the first semiconductor die. The conductive structure is formed by the first conductive via, the first conductive polymer liner, the second conductive via, and the second conductive polymer liner.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: April 9, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Yu-Han Hsueh
  • Patent number: 11953400
    Abstract: A pressure sensing unit is provided. The pressure sensing unit includes a membrane and a pressure sensing pad group. The membrane has a first surface and a second surface. The pressure sensing pad group includes a first pressure sensing pad, a second pressure sensing pad, and a ground pad that are spaced apart from one another. The ground pad and one among the first pressure sensing pad and the second pressure sensing pad are located at the first surface of the membrane, another one among the first pressure sensing pad and the second pressure sensing pad is located at the second surface of the membrane, and an orthographic projection of the ground pad projected onto a reference plane is located between orthographic projections of the first pressure sensing pad and the second pressure sensing pad that are projected onto the reference plane. Therefore, a signal-to-noise ratio can be increased and an erroneous detection can be prevented.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: April 9, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Che-Chia Hsu, Yu-Han Chen, Chi-Chieh Liao
  • Patent number: 11954179
    Abstract: Provided herein is a system and method to fuse data from sensors. The system includes sensors configured to capture data associated with one or more targets, the data including timestamps indicating originating times, one or more processors, and a memory storing instructions that, when executed by the one or more processors, causes the system to perform obtaining, at a filter, transmitted data associated with the one or more targets from the plurality of sensors, from the obtained data, identifying an unsequenced measurement having a timestamp before a second timestamp of a second measurement but obtained at the filter after the second measurement was obtained at the filter, updating a state of the filter according to the unsequenced measurement, based on a nonlinear measurement model and a nonlinear process model.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: April 9, 2024
    Assignee: Inceptio HONGKONG Limited
    Inventors: Yu Han, Yu Liu
  • Patent number: 11955547
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Publication number: 20240113089
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. The die has a front surface and a back surface opposite to the front surface. The underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. The patterned dielectric layer is disposed on the back surface of the die. The conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tian Hu, Po-Han Wang, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20240111078
    Abstract: A method forming a grating device includes: providing a substrate; entering the substrate into a process chamber; and depositing a grating material on the substrate to form a grating material layer on the substrate. A refractive index of the grating material gradually changes during depositing the grating material in the process chamber. The grating material layer includes a varying refractive index.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Chun-Wei HUANG, Yu-Shan TSAI, Po-Han FU
  • Patent number: 11948837
    Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fu Yeh, Chin-Lung Chung, Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
  • Patent number: 11948918
    Abstract: A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11946569
    Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Chung-Wei Kao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
  • Fan
    Patent number: 11946483
    Abstract: A fan is provided herein, including a housing, a hub, and a plurality of blades. The housing includes a top case and a bottom case. The hub is rotatably disposed between the top case and the bottom case in an axial direction. The blades extend from the hub in a radial direction, located between the top case and the bottom case. Each of the blades has a proximal end and a distal end. The proximal end is connected to the hub. The distal end is opposite from the proximal end, located at the other side of the blade, having at least one recessed portion. Each of the recessed portions form a passage for air.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: April 2, 2024
    Assignee: ACER INCORPORATED
    Inventors: Jau-Han Ke, Tsung-Ting Chen, Chun-Chieh Wang, Yu-Ming Lin, Cheng-Wen Hsieh, Wen-Neng Liao
  • Patent number: 11950428
    Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chen Wang, Meng-Han Lin, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
  • Patent number: 11950408
    Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 2, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Hsueh-Han Lu, Yu-Ting Lin
  • Publication number: 20240107023
    Abstract: A method of encoding video data includes determining an integer sample in a reference picture of the video data; determining, based on the integer sample, at least a first fractional sample and a second fractional sample, wherein the first fractional sample has a first fractional pel resolution, and the second fractional sample has a second fractional pel resolution different from the first fractional pel resolution; subsequent to determining both the first fractional sample and the second fractional sample, determining a first cost metric associated with the first fractional sample and a second cost metric associated with the second fractional sample; determining a reference block for a current block based on at least one of the first cost metric or the second cost metric; and encoding the current block based on the reference block.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: Yu Han, Vladan Andrijanic, Wei-Jung Chien, Cheng-Teh Hsieh, Marta Karczewicz
  • Publication number: 20240102025
    Abstract: The present disclosure provides a gene combination for expressing and producing terrequinone A in Escherichia coli and use thereof. The gene combination includes a tdiAS gene, a tdiBS gene, a tdiCS gene, a tdiDS gene, a tdiES gene, an sfpS gene, an ScCKS gene, and an AtIPKS gene with nucleotide sequences set forth in SEQ ID NOS:1 to 8. In the present disclosure, a recombinant engineered strain capable of producing terrequinone A having anti-cancer activity is obtained by separately constructing recombinant plasmids pC02 and pU03 through the eight genes and transforming the two recombinant plasmids into E. coli. The content of terrequinone A in a fermentation broth thereof is 106.3 mg/L, which has potential application value in the biopharmaceutical field.
    Type: Application
    Filed: May 24, 2023
    Publication date: March 28, 2024
    Inventors: Yongsheng TIAN, Lijuan WANG, Yongdong DENG, Quanhong YAO, Rihe PENG, Jianjie GAO, Zhenjun LI, Wenhui ZHANG, Bo WANG, Jing XU, Yu WANG, Xiaoyan FU, Hongjuan HAN