Patents by Inventor Yu-Hsiang Chen
Yu-Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088293Abstract: An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.Type: ApplicationFiled: October 5, 2022Publication date: March 14, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ya Chiu, Ssu-I Fu, Chin-Hung Chen, Jin-Yan Chiou, Wei-Chuan Tsai, Yu-Hsiang Lin
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Publication number: 20240085398Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Kun-Lung Chen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Jui-Cheng Huang
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Patent number: 11925457Abstract: A device for encouraging and guiding a spirometer user includes a housing, a main valve, a visual assembly, and a sound making assembly. The housing has a guiding channel, a first outlet channel, a second outlet channel, and an inlet channel. The main valve is disposed in a housing communicating with the guiding channel, the first outlet channel, the second outlet channel or the inlet channel and configured to regulate or control fluid flowing paths. The visual assembly includes a check valve in the second outlet channel, and at least one movable member. The sound making assembly includes a check valve and a sound maker. So, it can generate the visual and sound encouraging effects for learning how to use a spirometer correctly.Type: GrantFiled: February 17, 2021Date of Patent: March 12, 2024Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, CENTRAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Ming-Feng Wu, Yu-Hsuan Chen, Kuo-Chih Su, Chun-Hsiang Wang
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Patent number: 11920778Abstract: A ventilation fan includes a housing having an opening, a grille structure positioned to cover the opening, a fan module provided in the housing and a function module. The grille structure includes a base defining an outlet, and a grille support spaced apart from the base and connected by the connecting columns A radial inlet is formed between the base and the grille support is in communication with the outlet. The base includes a holder having a holding opening axially downward and faced away from the housing. The function module is disposed within the holder through the holding opening.Type: GrantFiled: September 30, 2022Date of Patent: March 5, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Yu-Hsiang Huang, Yen-Lin Chen, Chih-Hua Lin
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Patent number: 11923295Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a second dielectric layer on the high resistance layer, a low-k dielectric layer over the second dielectric layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.Type: GrantFiled: June 19, 2020Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hong-Wei Chan, Yung-Shih Cheng, Wen-Sheh Huang, Yu-Hsiang Chen
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Publication number: 20240071954Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20240071953Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20240063074Abstract: A semiconductor package is disclosed. The semiconductor package includes a package substrate. The semiconductor package includes a semiconductor die having a first surface attached to the package substrate and a second surface. The semiconductor package includes a heat sink attached to the second surface of the semiconductor die. The semiconductor package includes a heat dissipation layer interposed between the heat sink and the semiconductor die. The heat dissipation layer comprises one or more high-k dielectric materials.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Chen, Yu Hsiang Chen, Cheng Hung Wu, Wei-Pin Changchien, Ming-Fa Chen
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Publication number: 20240021494Abstract: A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.Type: ApplicationFiled: September 26, 2023Publication date: January 18, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Sheh HUANG, Yung-Shih CHENG, Jiing-Feng YANG, Yu-Hsiang CHEN, Chii-Ping CHEN
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Patent number: 11836295Abstract: A free space input standard is instantiated on a processor. Free space input is sensed and communicated to the processor. If the free space input satisfies the free space input standard, a touch screen input response is invoked in an operating system. The free space input may be sensed using continuous implicit, discrete implicit, active explicit, or passive explicit approaches. The touch screen input response may be invoked through communicating virtual touch screen input, a virtual input event, or a virtual command to or within the operating system. In this manner free space gestures may control existing touch screen interfaces and devices, without modifying those interfaces and devices directly to accept free space gestures.Type: GrantFiled: February 14, 2023Date of Patent: December 5, 2023Assignee: West Texas Technology Partners, LLCInventors: Shashwat Kandadai, Nathan Abercrombie, Yu-Hsiang Chen, Sleiman Itani
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Publication number: 20230369425Abstract: a transistor and an interconnect structure disposed over the transistor. The interconnect structure includes a first dielectric layer, a first conductive feature in the first dielectric layer, a first etch stop layer (ESL) disposed over the first dielectric layer and the first conductive feature, a dielectric feature disposed in the first ESL, an electrode disposed over the dielectric feature, and a second ESL disposed on the first ESL and the electrode.Type: ApplicationFiled: July 28, 2023Publication date: November 16, 2023Inventors: Yu-Hsiang Chen, Po-Hsiang Huang, Wen-Sheh Huang, Hsing-Leo Tsai, Chia-En Huang
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Patent number: 11798848Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure also includes a first conductive feature and a second conductive feature surrounded by the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element having a first portion over the second dielectric layer and a second portion penetrating through the second dielectric layer to be electrically connected to the first conductive feature. In addition, the semiconductor device structure includes a conductive via penetrating through the second dielectric layer to be electrically connected to the second conductive feature. The second portion of the resistive element is wider than the conductive via.Type: GrantFiled: December 21, 2021Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Sheh Huang, Hsiu-Wen Hsueh, Yu-Hsiang Chen, Chii-Ping Chen
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Patent number: 11799001Abstract: A transistor and an interconnect structure disposed over the transistor. The interconnect structure includes a first dielectric layer, a first conductive feature in the first dielectric layer, a first etch stop layer (ESL) disposed over the first dielectric layer and the first conductive feature, a dielectric feature disposed in the first ESL, an electrode disposed over the dielectric feature, and a second ESL disposed on the first ESL and the electrode.Type: GrantFiled: May 21, 2021Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hsiang Chen, Po-Hsiang Huang, Wen-Sheh Huang, Hsing-Leo Tsai, Chia-En Huang
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Publication number: 20230326795Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer and a first conductive feature and a second conductive feature surrounded by the first dielectric layer. The semiconductor device structure also includes a second dielectric layer over the first dielectric layer and a resistive element electrically connected to the first conductive feature. The second dielectric layer surrounds a portion of the resistive element. The semiconductor device structure further includes a conductive via electrically connected to the second conductive feature. The second dielectric layer surrounds a portion of the conductive via, and a contact area between the resistive element and the first conductive feature is wider than a contact area between the conductive via and the second conductive feature.Type: ApplicationFiled: June 12, 2023Publication date: October 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Sheh HUANG, Hsiu-Wen HSUEH, Yu-Hsiang CHEN, Chii-Ping CHEN
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Publication number: 20230307356Abstract: a first dielectric layer, a first conductive feature and a second conductive feature in the first dielectric layer, a first dielectric feature disposed directly on the first conductive feature; a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature, a first conductive layer disposed on and in contact with the first dielectric feature, a second ESL disposed over the first conductive layer, a second dielectric layer disposed directly on the first ESL and the second ESL, a first via extending through the second dielectric layer and the second ESL to contact with the first conductive feature, and a second via extending through the second dielectric layer and the first ESL to contact with the second conductive feature.Type: ApplicationFiled: March 24, 2022Publication date: September 28, 2023Inventors: Yu-Hsiang Chen, Wen-Sheh Huang, Po-Hsiang Huang, Hsiu-Wen Hsueh
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Publication number: 20230297173Abstract: A free space input standard is instantiated on a processor. Free space input is sensed and communicated to the processor. If the free space input satisfies the free space input standard, a touch screen input response is invoked in an operating system. The free space input may be sensed using continuous implicit, discrete implicit, active explicit, or passive explicit approaches. The touch screen input response may be invoked through communicating virtual touch screen input, a virtual input event, or a virtual command to or within the operating system. in this manner free space gestures may control existing touch screen interfaces and devices, without modifying those interfaces and devices directly to accept free space gestures.Type: ApplicationFiled: February 14, 2023Publication date: September 21, 2023Inventors: Shashwat Kandadai, Nathan Abercrombie, Yu-Hsiang Chen, Sleiman Itani
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Publication number: 20230268176Abstract: A semiconductor device structure and method for manufacturing the same are provided. The method includes forming a first resistive element over a substrate, and the first resistive element has a first sidewall extending in a first direction and a second sidewall opposite to the first sidewall and extending in the first direction. The method further includes forming a first conductive feature and a second conductive feature over and electrically connected to the first resistive element and forming a second resistive element over the first resistive element and spaced apart from the first resistive element in a second direction. In addition, the second resistive element is located between the first sidewall and the second sidewall of the first resistive element in a top view, and the first resistive element and the second resistive element are made of different nitrogen-containing materials.Type: ApplicationFiled: April 26, 2023Publication date: August 24, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Wen HSUEH, Yu-Hsiang CHEN, Wen-Sheh HUANG, Chii-Ping CHEN, Wan-Te CHEN
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Publication number: 20230251723Abstract: A method, system, apparatus, and/or device for moving or scrolling a virtual object in a virtual or augmented reality environment. The method, system, apparatus, and/or device may include: detecting, by a first sensor, a first gesture associated with selecting a first virtual object in an augmented reality environment displayed by a head-mounted display; displaying, by the head-mounted display, a first indicator indicating a selection of the first virtual object by a user; detecting, using the first sensor or a second sensor, a first movement of the head-mounted display associated with a first movement command; and in response to detecting the first movement of the head-mounted display, executing the first movement command, where the first movement command is a scrolling function to scroll text or a graphical object of the first virtual object or a movement function to move the text or the graphical object of the first virtual object.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Yu-Hsiang Chen, Soulaiman Itani
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Publication number: 20230173026Abstract: To prompt input and provide feedback on input to a user with an interface, inputs and graphical cursors associated with those inputs are defined. Each input may have several forms such as base, hover, engaged, completed, and error. User input is anticipated. The base form of the anticipated input cursor is displayed to prompt the user for the anticipated input. If user hover is detected that matches anticipated input, the hover form is displayed to confirm the match to the user. If user input is detected that matches anticipated input, the engaged form is displayed as confirmation. If user input is completed that matches anticipated input, the completed form is displayed as confirmation. If user hover or input does not match anticipated input, the error form is displayed to indicate mismatch. Not all cursors must have all forms, and some cursors may have multiples of some forms.Type: ApplicationFiled: October 8, 2022Publication date: June 8, 2023Inventors: Sleiman Itani, Yu-Hsiang Chen, Mohamed Nabil Hajj Chehade, Allen Yang Yang
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Patent number: 11670501Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.Type: GrantFiled: March 31, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Wen Hsueh, Yu-Hsiang Chen, Wen-Sheh Huang, Chii-Ping Chen, Wan-Te Chen