Patents by Inventor Yu-Hsiang Wang
Yu-Hsiang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11824966Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals. The multiplexer, coupled to the serializer, is configured to selectively output the series of command signals or the series of data signals.Type: GrantFiled: January 31, 2021Date of Patent: November 21, 2023Assignee: NOVATEK Microelectronics Corp.Inventors: Yong-Ren Fang, Yu-Hsiang Wang, Che-Wei Yeh
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Publication number: 20230370750Abstract: An image sensor and an operating method thereof are provided. The image sensor includes a first pixel circuit, a first column readout circuit, and a second column readout circuit. The first pixel circuit includes a first pixel unit, a first transfer transistor, a first reset transistor, a first readout transistor, and a first capacitor. The first column readout circuit includes a first circuit node. The second column readout circuit includes a bias transistor. A first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first readout transistor is coupled to the bias transistor.Type: ApplicationFiled: April 20, 2023Publication date: November 16, 2023Applicant: Guangzhou Tyrafos Semiconductor Technologies Co., LTDInventors: Ping-Hung Yin, Jia-Shyang Wang, Yu-Hsiang Wang
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Patent number: 11749168Abstract: The disclosure provides a data receiver, including a first capacitor, a second capacitor, a first inverter and a second inverter. The first capacitor has a first terminal and a second terminal, and the first terminal receives a first input signal. The second capacitor has a third terminal and a fourth terminal, and the third terminal receives a second input signal. The first inverter has a first input terminal and a first output terminal. The second inverter has a second input terminal and a second output terminal. The first input terminal and the second output terminal are coupled to the second terminal of the first capacitor, and the second input terminal and the first output terminal are coupled to the fourth terminal of the second capacitor. The first output terminal generates a first output signal with a first output voltage, and the second output terminal generates a second output signal with a second output voltage.Type: GrantFiled: July 4, 2022Date of Patent: September 5, 2023Assignee: Novatek Microelectronics Corp.Inventors: Ho-Chun Chang, Che-Wei Yeh, Yu-Hsiang Wang, Keko-Chun Liang
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Publication number: 20230005451Abstract: A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.Type: ApplicationFiled: September 14, 2022Publication date: January 5, 2023Applicant: NOVATEK Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu, Yi-Yang Tsai, Po-Hsiang Fang
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Patent number: 11545081Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N?1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N?1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.Type: GrantFiled: April 14, 2022Date of Patent: January 3, 2023Assignee: Novatek Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu
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Patent number: 11527195Abstract: A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.Type: GrantFiled: April 22, 2021Date of Patent: December 13, 2022Assignee: NOVATEK Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu
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Patent number: 11509296Abstract: A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.Type: GrantFiled: April 25, 2021Date of Patent: November 22, 2022Assignee: NOVATEK Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yi-Chuan Liu
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Publication number: 20220345123Abstract: A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.Type: ApplicationFiled: April 25, 2021Publication date: October 27, 2022Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yi-Chuan Liu
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Publication number: 20220343833Abstract: A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu
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Patent number: 11482293Abstract: A control system includes a plurality of driving circuits coupled in series, which includes a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a replica receiver. The first transmitter is coupled to the first receiver, and the replica receiver is coupled to an output terminal of the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver and a second transmitter. The second receiver is coupled to the first transmitter, and the second transmitter is coupled to the second receiver.Type: GrantFiled: June 30, 2021Date of Patent: October 25, 2022Assignee: NOVATEK Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu, Yi-Yang Tsai, Po-Hsiang Fang
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Patent number: 11430382Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.Type: GrantFiled: August 24, 2021Date of Patent: August 30, 2022Assignee: Novatek Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Po-Hsiang Fang, Ju-Lin Huang
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Publication number: 20220254305Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N?1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N?1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.Type: ApplicationFiled: April 14, 2022Publication date: August 11, 2022Applicant: Novatek Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu
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Publication number: 20220220644Abstract: A warp scheduling method includes: storing plural of first warps issued to a streaming multiprocessor in an instruction buffer module; marking plural of second warps which are able to be scheduled in the first warps by a schedulable warp indication window, wherein the number of the marked second warps is the size of the schedulable warp indication window; sampling the read/storage unit stall cycle in each time interval to obtain a read/storage unit stall cycle proportion; comparing the read/storage unit stall cycle proportion with the stall cycle threshold, and adjusting the size of the schedulable warp indication window and determining the second warps according to the comparison result; issuing the second warps from the instruction buffer module to a corresponding one of the processing modules for execution.Type: ApplicationFiled: April 12, 2021Publication date: July 14, 2022Applicant: NATIONAL CHENG KUNG UNIVERSITYInventors: Chung-ho CHEN, Chien-ming CHIU, Yu-hsiang WANG
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Patent number: 11367390Abstract: A display apparatus and a method for noise reduction are introduced. The method comprises steps of sensing a first pixel signal being superimposed by noises from a first pixel through a first sensing line in a first phase of a sensing operation and sensing a first noise signal from the first sensing line in a second phase of the sensing operation. The method further comprises steps of sensing a second noise signal from a second sensing line in the first phase of the sensing operation, and sensing a third noise signal from the second sensing line in the second phase of the sensing operation. The method further removes the noises that are superimposed to the first pixel signal according to a difference between the first pixel signal and the first noise signal and a difference between the second noise signal and the third noise signal to generate a denoised sensing value of the first pixel.Type: GrantFiled: June 2, 2019Date of Patent: June 21, 2022Assignee: Novatek Microelectronics Corp.Inventors: Keko-Chun Liang, Yu-Hsiang Wang, Jhih-Siou Cheng, Yi-Chuan Liu, Ju-Lin Huang
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Patent number: 11341904Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N?1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N?1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.Type: GrantFiled: December 30, 2020Date of Patent: May 24, 2022Assignee: Novatek Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu
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Publication number: 20220044748Abstract: A control system includes a plurality of driving circuits coupled in series, which includes a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a replica receiver. The first transmitter is coupled to the first receiver, and the replica receiver is coupled to an output terminal of the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver and a second transmitter. The second receiver is coupled to the first transmitter, and the second transmitter is coupled to the second receiver.Type: ApplicationFiled: June 30, 2021Publication date: February 10, 2022Applicant: NOVATEK Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu, Yi-Yang Tsai, Po-Hsiang Fang
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Publication number: 20220006608Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals.Type: ApplicationFiled: January 31, 2021Publication date: January 6, 2022Inventors: Yong-Ren Fang, Yu-Hsiang Wang, Che-Wei Yeh
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Publication number: 20210383749Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.Type: ApplicationFiled: August 24, 2021Publication date: December 9, 2021Applicant: Novatek Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Po-Hsiang Fang, Ju-Lin Huang
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Patent number: 11170702Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.Type: GrantFiled: August 27, 2020Date of Patent: November 9, 2021Assignee: Novatek Microelectronics Corp.Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Po-Hsiang Fang, Ju-Lin Huang
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Patent number: 11088818Abstract: A receiver is configured to receive a series of command signals and a series of data signals. The receiver includes a first clock and data recovery (CDR) circuit, a control circuit and a second CDR circuit. The first CDR circuit is configured to process the series of command signal to generate a clock signal. The control circuit, coupled to the first CDR circuit, is configured to generate a control signal according to the series of command signals and the clock signal received from the first CDR circuit. The second CDR circuit, coupled to the control circuit, is configured to process the series of data signals according to the control signal received from the control circuit.Type: GrantFiled: July 1, 2020Date of Patent: August 10, 2021Assignee: NOVATEK Microelectronics Corp.Inventors: Yong-Ren Fang, Yu-Hsiang Wang, Che-Wei Yeh