Abstract: A wearable device includes a ground element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, and a fifth radiation element. The first radiation element has a feeding point, and is coupled to a first grounding point on the ground element. A slot region is surrounded by the first radiation element and the ground element. The second radiation element is coupled to a second grounding point on the ground element. The third radiation element is coupled to the second grounding point. The third radiation element and the second radiation element substantially extend in opposite directions. The fourth radiation element and the fifth radiation element are disposed inside the slot region. An antenna structure is formed by the first radiation element, the second radiation element, the third radiation element, the fourth radiation element, and the fifth radiation element.

Abstract: An antenna structure includes a ground element, a first radiation element, a second radiation element, a third radiation element, and a nonconductive support element. The first radiation element is coupled to a first grounding point on the ground element. The second radiation element has a feeding point. The second radiation element is adjacent to the first radiation element. The third radiation element is coupled to a second grounding point on the ground element. The third radiation element is adjacent to the second radiation element. The first radiation element, the second radiation element, and the third radiation element are disposed on the nonconductive support element. The second radiation element is at least partially surrounded by the first radiation element. The third radiation element is at least partially surrounded by the second radiation element.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A rotary seat including a base includes an outer surface, and a composite material layer attached to at least a part of the outer surface. The base also includes a recess for accommodating a turntable and including a first opening on the outer surface. The material of the composite material layer includes fibers and a resin. Therefore, the rotary seat may be more lightweight. A rotary table is also provided and includes the rotary seat, a driving device which drives the rotary seat to rotate, and a turntable which is rotatably disposed in the recess of the base.

Abstract: Disclosed herein are devices and methods to reduce unwanted CIM3 emission in a wireless communication device, such that the transmit (TX) power level applied in a RU can be increased without exceeding a regulatory emission requirement. In some aspects, unwanted emission may be reduced by shifting or changing local oscillator (LO) frequencies during TX operation. Some embodiments are directed to a fast-locking PLL with adjustable bandwidth that can be controlled to increase the PLL bandwidth during the RX to TX transition to provide a fast locking to a new LO frequency. Some aspects are directed to configuring an LO frequency shift amount for different RUs when multiple RUs are allocated within a frequency band.

Abstract: A compensator compensates for the distortions of a power amplifier circuit. A power amplifier neural network (PAN) is trained to model the power amplifier circuit using pre-determined input and output signal pairs that characterize the power amplifier circuit. Then a compensator is trained to pre-distort a signal received by the PAN. The compensator uses a neural network trained to optimize a loss between a compensator input and a PAN output, and the loss is calculated according to a multi-objective loss function that includes one or more time-domain loss function and one or more frequency-domain loss functions. The trained compensator performs signal compensation to thereby output a pre-distorted signal to the power amplifier circuit.

Abstract: A multi-user downlink orthogonal frequency-division multiple access (OFDMA) configuration method includes: assigning contiguous resource units (RUs) included in a channel to a plurality of stations, respectively; and assigning, by an access point (AP), one modulation and coding scheme (MCS) to each of the plurality of stations. Data rates of modulation and coding schemes that are assigned to first stations and associated with contiguous first RUs assigned to the first stations are monotonic, where the first stations are included in the plurality of stations.

Abstract: A transmitter including two radio transceivers and a controller is provided. The first radio transceiver supports a first number of Spatial Streams (SS) for a first Transmission (Tx) opportunity of wireless transmission to a receiver. The second radio transceiver supports a second number of SS for a second Tx opportunity of wireless transmission to the receiver. The first Tx opportunity starts earlier than the second Tx opportunity. The controller determines whether the power consumption of SS utilization in the first and second Tx opportunities exceeds a threshold, and if so, performs one of the following: deferring the second Tx opportunity until the first Tx opportunity ends; and aborting the first Tx opportunity when the second Tx opportunity starts.

Abstract: A communications apparatus includes a plurality of communications circuits and a coexistence management circuit. Each communications circuit is configured to provide wireless communications services in compliance with a protocol. The coexistence management circuit is configured to manage radio activities of the communications circuits. In response to a detection result of at least two radio activities to occur in a subsequent packet time, the coexistence management circuit is configured to determine whether an interference signal related to said at least two radio activities falls in a predetermined frequency band, and when the interference signal falls in the predetermined frequency band, the coexistence management circuit is configured to adjust a transmission power or an execution time of one of said at least two radio activities.

Abstract: A calibration apparatus is used for calibrating characteristics of a power amplifier (PA) in a transmitter. The calibration apparatus includes an adaptive bias generator circuit that is used to track an envelope of an input signal received by control terminals of transistors of the PA and generate an adaptive bias voltage to the control terminals of the input transistors in response to the envelope of the input signal.

Abstract: Disclosed herein are devices and methods to reduce unwanted CIMS emission in a wireless communication device, such that the transmit (TX) power level applied in a RU can be increased without exceeding a regulatory emission requirement. In some aspects, unwanted emission may be reduced by shifting or changing local oscillator (LO) frequencies during TX operation. Some embodiments are directed to a fast-locking PLL with adjustable bandwidth that can be controlled to increase the PLL bandwidth during the RX to TX transition to provide a fast locking to a new LO frequency. Some aspects are directed to configuring an LO frequency shift amount for different RUs when multiple RUs are allocated within a frequency band.