Patents by Inventor Yu-Hsien Chin
Yu-Hsien Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9082787Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: GrantFiled: December 23, 2013Date of Patent: July 14, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Publication number: 20140106519Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: ApplicationFiled: December 23, 2013Publication date: April 17, 2014Applicant: Macronix International Co., Ltd.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8691653Abstract: A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.Type: GrantFiled: March 5, 2012Date of Patent: April 8, 2014Assignee: Macronix International Co., Ltd.Inventors: Chih-Chia Hsu, Yu-Hsien Chin, Yin-Fu Huang
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Patent number: 8659080Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: GrantFiled: March 5, 2012Date of Patent: February 25, 2014Assignee: Macronix International Co., Ltd.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8586442Abstract: A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.Type: GrantFiled: November 28, 2012Date of Patent: November 19, 2013Assignee: Macronix International Co. Ltd.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Publication number: 20130228861Abstract: A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.Type: ApplicationFiled: March 5, 2012Publication date: September 5, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Chia Hsu, Yu-Hsien Chin, Yin-Fu Huang
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Publication number: 20130228831Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: ApplicationFiled: March 5, 2012Publication date: September 5, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8367511Abstract: A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.Type: GrantFiled: March 7, 2011Date of Patent: February 5, 2013Assignee: Macronix International Co., Ltd.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Publication number: 20120231597Abstract: A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.Type: ApplicationFiled: March 7, 2011Publication date: September 13, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang