Patents by Inventor Yu Hsien Wang
Yu Hsien Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996165Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.Type: GrantFiled: May 17, 2022Date of Patent: May 28, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsien Yang, Yu-Chih Wang, Kuo-Hsiang Chen
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Publication number: 20240161818Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.Type: ApplicationFiled: November 30, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Li-Ping Huang, Yu-Fang Chen, Chun-Yen Tseng, Tzu-Feng Chang, Chun-Chieh Chang
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Patent number: 11968908Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.Type: GrantFiled: June 30, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
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Patent number: 11955547Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.Type: GrantFiled: December 20, 2018Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
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Publication number: 20240112957Abstract: A fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.Type: ApplicationFiled: January 12, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Xuan Wang, Cheng-Chun Tseng, Yi-Chun Chen, Yu-Hsien Lin, Ryan Chia-Jen Chen
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Patent number: 11946771Abstract: An aerial vehicle including a body, a first ranging device, a second ranging device and a controller is provided. The first ranging device is disposed on the body and is configured to detect a first distance between the first ranging device and the reflector. The second ranging device is disposed on the body and is configured to detect a second distance between the second ranging device and the reflector. The controller is configured to obtain an included angle between a direction of the body and the reflector according to the first distance and the second distance.Type: GrantFiled: April 1, 2020Date of Patent: April 2, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yuan-Chu Tai, Chung-Hsien Wu, Yu-Kai Wang
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Patent number: 11943935Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.Type: GrantFiled: September 26, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
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Publication number: 20240096630Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.Type: ApplicationFiled: January 12, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Jih-Sheng Yang, Shih-Chieh Chao, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20240072170Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Yih-Ann Lin, Chia Ming Liang, Ryan Chia-Jen CHEN
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Patent number: 11915755Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.Type: GrantFiled: January 20, 2022Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
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Patent number: 11916314Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.Type: GrantFiled: May 12, 2022Date of Patent: February 27, 2024Assignee: HTC CorporationInventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
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Patent number: 10493602Abstract: A compressing apparatus has a compressing jig and a pressing device. The compressing jig has a lower compressing assembly and an upper compressing assembly. The lower compressing assembly has a lower mount with at least one pitching plate and at least one limiting set. Each one of the at least one limiting set has multiple poles disposed around a corresponding pitching plate. Each one of the multiple poles has a top end higher than the corresponding pitching plate and a limiting indention disposed at the top end with a supporting portion disposed at a same height with the corresponding pitching plate. The upper compressing assembly has at least one clamping plate respectively aligned with the at least one pitching plate and being movable up and down. The pressing device has a base with a receiving space to receive the upper compressing assembly.Type: GrantFiled: November 2, 2017Date of Patent: December 3, 2019Assignee: Horng Terng Automation Co., Ltd.Inventor: Yu Hsien Wang
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Publication number: 20190061111Abstract: A compressing apparatus has a compressing jig and a pressing device. The compressing jig has a lower compressing assembly and an upper compressing assembly. The lower compressing assembly has a lower mount with at least one pitching plate and at least one limiting set. Each one of the at least one limiting set has multiple poles disposed around a corresponding pitching plate. Each one of the multiple poles has a top end higher than the corresponding pitching plate and a limiting indention disposed at the top end with a supporting portion disposed at a same height with the corresponding pitching plate. The upper compressing assembly has at least one clamping plate respectively aligned with the at least one pitching plate and being movable up and down. The pressing device has a base with a receiving space to receive the upper compressing assembly.Type: ApplicationFiled: November 2, 2017Publication date: February 28, 2019Inventor: Yu Hsien Wang
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Patent number: 7596655Abstract: A flash storage comprises a flash memory, including a plurality of physical memory blocks, each of physical memory blocks comprising a plurality of memory segments, and a plurality of physical sectors, and each of physical sectors being further provided therein with at least a user data column and a logical address pointer column. When physical data is written into the user data column, writing logical address pointer data into the logical address pointer column of the same physical sector may be performed together by the control of a micro-controller. Furthermore, the logical address pointer data in the same memory segment are arranged to be a backup memory segment address mapping table and then stored in one physical memory block. The backup memory segment address mapping table may be loaded directly and stored into a registered memory by the micro-controller when the system boots.Type: GrantFiled: March 7, 2006Date of Patent: September 29, 2009Assignee: Prolific Technology Inc.Inventors: Yu-Hsien Wang, Chanson Lin, Tung-Hsien Wu, Chien-Chang Su, Gow-Jeng Lin, Ching-Chung Hsu, Kuang-Yuan Chen
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Patent number: 7382423Abstract: A backlight module is applied to a liquid crystal display device. The liquid crystal display device includes an optical film set having at least one optical film. The optical film set is disposed above the backlight module. The backlight module includes a housing and a spacer. The housing has a bottom plate provided with a through opening, an inward side and an outward side, wherein the inward side faces the optical film and the outward side is opposite to the inward side. The spacer supports the optical film set and is mounted onto the bottom plate of the backlight module from the outward side of the bottom plate.Type: GrantFiled: October 5, 2004Date of Patent: June 3, 2008Assignee: Hannstar Display Corp.Inventors: Ke Chin Chang, Fu Tung Chen, Yu Hsien Wang
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Publication number: 20060271727Abstract: A flash storage comprises a flash memory, including a plurality of physical memory blocks, each of physical memory blocks comprising a plurality of memory segments, and a plurality of physical sectors, and each of physical sectors being further provided therein with at least a user data column and a logical address pointer column. When physical data is written into the user data column, writing logical address pointer data into the logical address pointer column of the same physical sector may be performed together by the control of a micro-controller. Furthermore, the logical address pointer data in the same memory segment are arranged to be a backup memory segment address mapping table and then stored in one physical memory block. The backup memory segment address mapping table may be loaded directly and stored into a registered memory by the micro-controller when the system boots.Type: ApplicationFiled: March 7, 2006Publication date: November 30, 2006Inventors: Yu-Hsien Wang, Chanson Lin, Tung-Hsien Wu, Chien-Chang Su, Gow-Jeng Lin, Ching-Chung Hsu, Kuang-Yuan Chen
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Publication number: 20060161767Abstract: An execution method and architecture of multiple-program-banks firmware are proposed. The firmware is divided into multiple program banks stored in a nonvolatile memory. The program banks are also stored in a RAM. A No1 Bank manages the execution of these program banks. Programs of the program banks and updated codes of common programs can be modified at any time via an external interface bus. The execution method and architecture of multiple-program-banks firmware can accomplish better performance of program execution, and can change the content of a firmware program to enhance the flexibility of firmware.Type: ApplicationFiled: February 8, 2005Publication date: July 20, 2006Inventors: Yu-Hsien Wang, Chanson Lin, Hunk Hung
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Publication number: 20060114728Abstract: A data storage device having multiple buffers is proposed. When storing data, a controller makes use of a host's bus to select and transmit multiple block data to multiple buffers for temporary storage and then records relevant details. Next, the controller transmits the data from the buffers to a storage connected with the controller. When retrieving data, the controller selects the data from the storage and temporarily stores the data in the buffers and then records relevant details. Subsequently, the controller transmits the data to the host. The controller is used to control the operations of the host, the buffers, and the storage. Multiple buffers are exploited to achieve the maximum bandwidth of the transmission interface of the host to increase the transmission speed.Type: ApplicationFiled: February 1, 2005Publication date: June 1, 2006Inventors: Chanson Lin, Yu-Hsien Wang, Hung Huang, Po Fan