Patents by Inventor YU-HSIN PAN

YU-HSIN PAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Carrier board structure with an increased core-layer trace area and method for manufacturing same
    Patent number: 11497115
    Abstract: Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 8, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Yi Lin, Hsiao-Han Huang, Yu-Hsin Pan
  • CARRIER BOARD STRUCTURE WITH AN INCREASED CORE-LAYER TRACE AREA AND METHOD FOR MANUFACTURING SAME
    Publication number: 20210378092
    Abstract: Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.
    Type: Application
    Filed: July 31, 2020
    Publication date: December 2, 2021
    Inventors: YI LIN, HSIAO-HAN HUANG, YU-HSIN PAN