Patents by Inventor Yu-Hsuan Lin

Yu-Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11943609
    Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device generates a first resolvable set identifier corresponding to the first member device, and generates and transmits target Bluetooth packets containing the first resolvable set identifier to the Bluetooth host device. The second member device generates a resolvable set identifier corresponding to the second member device according to a device set identification information. The Bluetooth host device identifies the first member device as a first privileged device according to the position of the first resolvable set identifier, and transmits a first privileged pairing notice to the first member device and generates a first cypher key. The first member device further generates a second cypher key corresponding to the first cypher key after receiving the first privileged pairing notice.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 26, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yu Hsuan Liu, Yung Chieh Lin, Po Sheng Chiu
  • Publication number: 20240096806
    Abstract: A method for manufacturing a semiconductor structure is provided. A substrate including a fin structure is received, provided or formed. A sacrificial gate layer is formed over the fin structure and a source/drain structure is formed adjacent to the sacrificial gate layer, wherein the sacrificial gate layer is surrounded by a dielectric structure. The sacrificial gate layer is removed, wherein a recess is defined by the dielectric structure. A work function layer is formed in the recess, wherein the work function layer includes an overhang portion at an opening of the recess. A thickness of the work function layer is reduced. A glue layer is formed over the work function layer. A semiconductor structure thereof is also provided.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 21, 2024
    Inventors: CHAO-HSUAN CHEN, WEI CHEN HUNG, LI-WEI YIN, YU-HSIEN LIN, YIH-ANN LIN, RYAN CHIA-JEN CHEN
  • Patent number: 11937366
    Abstract: A method of a circuit signal enhancement of a circuit board comprises the following steps: forming a first substrate body with a first signal transmission circuit layer and a second substrate body with a second signal transmission circuit layer; forming a first signal enhancement circuit layer and a second signal enhancement circuit layer on the first substrate body and the second substrate body; forming a third substrate body with a third signal transmission circuit layer and a fourth substrate body with a fourth signal transmission circuit layer on the carrier; separating the third substrate body and the fourth substrate body from the carrier; combining the first signal transmission circuit layer and the third signal transmission circuit layer through the first signal enhancement circuit layer; and combining the second signal transmission circuit layer and the fourth signal transmission circuit layer through the second signal enhancement circuit layer.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: March 19, 2024
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tzu Hsuan Wang, Yu Cheng Lin
  • Publication number: 20240088307
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240087933
    Abstract: A wafer transporting method includes following operations. A plurality of wafers are received in a semiconductor container attached to a mobile vehicle. An air processing system is coupled to a wall of the semiconductor container. The air processing system includes an inlet valve, an outlet valve, a pump between the inlet valve and the outlet valve, and a desiccant coupled to the pump. The semiconductor container is moved. The pump of the air processing system is turned on to extract air from inside the semiconductor container into the air processing system through the inlet valve. Humidity of the air is reduced when the air passes through the desiccant of the air processing system. The air is returned back to the semiconductor container through the outlet valve.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: YOU-CHENG YEH, MAO-CHIH HUANG, YEN-CHING HUANG, YU HSUAN CHUANG, TAI-HSIANG LIN, JIAN-SHIAN LIN
  • Publication number: 20240090238
    Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Feng-Min LEE, Erh-Kun LAI, Dai-Ying LEE, Yu-Hsuan LIN, Po-Hao TSENG, Ming-Hsiu LEE
  • Publication number: 20240087953
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240077762
    Abstract: A display is disclosed. The display comprises a display panel, and an optical film disposed on a viewing side of the display panel. The optical film has a total haze ranging from 15% to 60%, an inner haze less than or equal to 10%, and a reflectivity satisfying the relationships of 0.35%?(RSCI-RSCE)?1.50% and RSCE?1.50%, wherein RSCI is an average reflectivity of diffuse component and specular component, and RSCE is an average reflectivity of diffuse component. By adjusting the total haze, inner haze and reflectivity of the optical film to satisfy the above relationship, the display can have good anti-glare properties, and the contrast ratio of the display will not be reduced too much to avoid the display quality be affected.
    Type: Application
    Filed: April 10, 2023
    Publication date: March 7, 2024
    Applicant: BenQ Materials Corporation
    Inventors: Yu-Wei Tu, Chih-Wei Lin, Kuo-Hsuan Yu
  • Patent number: 11921474
    Abstract: A virtual metrology method using a convolutional neural network (CNN) is provided. In this method, a dynamic time warping (DTW) algorithm is used to delete unsimilar sets of process data, and adjust the sets of process data to be of the same length, thereby enabling the CNN to be used for virtual metrology. A virtual metrology model of the embodiments of the present invention includes several CNN models and a conjecture model, in which plural inputs of the CNN model are sets of time sequence data of respective parameters, and plural outputs of the CNN models are inputs to the conjecture model.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 5, 2024
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Fan-Tien Cheng, Yu-Ming Hsieh, Tan-Ju Wang, Li-Hsuan Peng, Chin-Yi Lin
  • Patent number: 11924631
    Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The Bluetooth host device controls a display device to display a candidate device list, and to display a single device item in the candidate device list to represent the Bluetooth device set, but does not simultaneously display two device items in the candidate device list to represent the first member device and the second member device. The Bluetooth host device generates a first cypher key according to an instruction from the first member device and a device information of the first member device after receiving a selection command. The first member device establishes a connection with the Bluetooth host device, and generates a second cypher key corresponding to the first cypher key according to a device information of the Bluetooth host device.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 5, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yu Hsuan Liu, Yung Chieh Lin, Po Sheng Chiu
  • Publication number: 20240071981
    Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
  • Publication number: 20240069069
    Abstract: A probe pin cleaning pad including a foam layer, a cleaning layer, and a polishing layer is provided. The cleaning layer is disposed between the foam layer and the polishing layer. A cleaning method for a probe pin is also provided.
    Type: Application
    Filed: November 10, 2023
    Publication date: February 29, 2024
    Applicant: Alliance Material Co., Ltd.
    Inventors: Chun-Fa Chen, Yu-Hsuen Lee, Ching-Wen Hsu, Chao-Hsuan Yang, Ting-Wei Lin
  • Publication number: 20240067746
    Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 29, 2024
    Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
  • Patent number: 11875849
    Abstract: An analog content-address memory (analog CAM) having approximation matching and an operation method thereof are provided. The analog CAM includes an inputting circuit, at least one analog CAM cell and an outputting circuit. The inputting circuit is configured to provide an inputting data. The analog CAM cell is connected to the inputting circuit and receives the inputting data. The analog CAM cell has a mild swing match curve whose highest point corresponds to a stored data. A segment from the highest point of the mild swing match curve to a lowest point of the mild swing match curve corresponds to at least three data values. The outputting circuit is connected to the analog CAM cell and receives a match signal from the analog CAM cell. The outputting circuit outputs a match approximation level according to the match signal.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: January 16, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsuan Lin, Po-Hao Tseng, Feng-Min Lee
  • Patent number: 11871588
    Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: January 9, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Feng-Min Lee, Erh-Kun Lai, Dai-Ying Lee, Yu-Hsuan Lin, Po-Hao Tseng, Ming-Hsiu Lee
  • Publication number: 20240000983
    Abstract: A microbial inhibition device for inhibiting microorganisms on a predetermined object includes: a covering member covering the predetermined object, and having an attachment surface for attaching to the predetermined object, and an exposed surface opposite to the attachment surface, wherein the covering member includes at least a conductive medium layer, and the conductive medium layer constitutes a predetermined area of the exposed surface; a control module configured to issue a control command reflecting a predetermined conduction mode; and a power supply module electrically connected to the conductive medium layer, and configured to receive the control command so as to power the conductive medium layer according to the predetermined conduction mode based on the control command. The conductive medium layer is conducted with current according to the predetermined conduction mode through the power supply module. Accordingly predetermined microorganisms on the predetermined area are inhibited or killed.
    Type: Application
    Filed: January 31, 2023
    Publication date: January 4, 2024
    Inventors: HSIN-YI TSAI, YU-HSUAN LIN, CHUN-HAN CHOU, KUO-CHENG HUANG, CHING-CHING YANG
  • Patent number: 11853890
    Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 26, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chao-Hung Wang, Yu-Hsuan Lin, Ming-Liang Wei, Dai-Ying Lee
  • Publication number: 20230410904
    Abstract: The application provides a content addressable memory (CAM) memory device, a CAM cell and a method for searching and comparing data thereof. The CAM device includes: a plurality of CAM cells; and an electrical characteristic detection circuit coupled to the CAM cells; wherein in data searching, a search data is compared with a storage data stored in the CAM cells, the CAM cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Inventors: Yu-Hsuan LIN, Po-Hao TSENG
  • Publication number: 20230395669
    Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece having a channel region, a gate structure over the channel region, gate spacers extending along sidewalls of the gate structure, and an etch stop layer extending along sidewalls of the gate spacers. The method also includes performing an etching process to recess the gate spacers and the gate structure, thereby forming a funnel-shaped trench, depositing a dielectric layer over the workpiece to partially fill the funnel-shaped trench, etching back the dielectric layer to form dielectric spacers on the recessed gate spacers, forming a metal cap on the gate structure without forming the metal cap on the recessed gate spacers, and forming a dielectric cap on the metal cap.
    Type: Application
    Filed: June 4, 2022
    Publication date: December 7, 2023
    Inventors: Yu-Hsuan Lin, Chun Po Chang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Jian-Hao Chen