Patents by Inventor Yu-Hsuan Tsai
Yu-Hsuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178847Abstract: The present disclosure discloses a media communication apparatus having built-in signal synchronization mechanism. A local clock generation circuit generates a reference clock signal and a media clock signal. A time calibration circuit performs time calibration process with an external apparatus to generate time calibration information to further calibrate the reference clock signal and the media clock signal accordingly to generate a calibrated reference clock signal and a calibrated media clock signal on a standard time domain. A media clock processing circuit generates a sampling signal according to the calibrated media clock signal. A signal processing circuit generates time related information according to the calibrated reference clock signal to process an input media signal according to the time related information and the sampling signal and generate an output media signal.Type: ApplicationFiled: November 16, 2023Publication date: May 30, 2024Inventors: MING-JHE DU, Ming-Hsuan Tsai, Chun-I Yeh, Yu-Chong Yen
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Patent number: 11990381Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.Type: GrantFiled: November 14, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
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Publication number: 20240161343Abstract: An image processing method includes following operations: receiving, by a processor, an input image from a camera; performing, by the processor, a top-view calibration process to generate a top-view calibrated image according to the input image; performing, by the processor, an object extraction process on the top-view calibrated image to generate at least one target object frame; performing, by the processer, a centering process on the at least one target object frame to generate a centered image; and outputting, by the processor, the centered image for a display panel to display.Type: ApplicationFiled: June 7, 2023Publication date: May 16, 2024Inventors: Yi-Hsuan HUANG, Yao-Jia KUO, Yu-Chi TSAI, Wen-Tsung HUANG
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Patent number: 11947886Abstract: A development system and a method of an offline software-in-the-loop simulation are disclosed. A common firmware architecture generates a chip control program. The common firmware architecture has an application layer and a hardware abstraction layer. The application layer has a configuration header file and a product program. A processing program required by a peripheral module is added to the hardware abstraction layer during compiling. The chip control program is provided to a controller chip or a circuit simulation software to be executed to control the product-related circuit through controlling the peripheral module.Type: GrantFiled: June 28, 2022Date of Patent: April 2, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Yu-Jen Lin, Chang-Chung Lin, Chia-Wei Chu, Terng-Wei Tsai, Feng-Hsuan Tung
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Publication number: 20240088307Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Patent number: 11929318Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.Type: GrantFiled: May 10, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Publication number: 20240075082Abstract: Provided is a composition including a lactic acid bacterium and a carrier thereof for prophylaxis or treatment of an allergy. The lactic acid bacterium is Lactobacillus paragasseri, such as Lactobacillus paragasseri BBM171 deposited under DSMZ Accession No. DSM 34311. Also provided is a method for preventing or treating an allergy in a subject that includes administering an effective amount of the composition of Lactobacillus paragasseri to the subject.Type: ApplicationFiled: August 24, 2023Publication date: March 7, 2024Inventors: Ying-Chieh Tsai, Yu-Hsuan Wei, Chih-Chieh Hsu, Chien-Chen Wu
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Patent number: 11920020Abstract: A composite material including a nanocellulose core and a metal shell is provided. The metal shell covers a surface of the nanocellulose core. The composite material is nanosized and has high mechanical strength. Additionally, a method of manufacturing the composite material is also provided.Type: GrantFiled: December 11, 2020Date of Patent: March 5, 2024Assignee: Winbond Electronics Corp.Inventors: Ming-Chih Tsai, Yu-Hsuan Ho
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Publication number: 20240071981Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.Type: ApplicationFiled: November 1, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
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Patent number: 11565934Abstract: A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.Type: GrantFiled: January 3, 2020Date of Patent: January 31, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Hsuan Tsai, Lu-Ming Lai, Chien-Wei Fang, Ching-Han Huang
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Patent number: 11174157Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.Type: GrantFiled: June 25, 2019Date of Patent: November 16, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: Chi Sheng Tseng, Lu-Ming Lai, Yu-Hsuan Tsai, Yin-Hao Chen, Hsin Lin Wu, San-Kuei Yu
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Patent number: 11101189Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.Type: GrantFiled: May 27, 2020Date of Patent: August 24, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ming Yen Lee, Chia-Hao Sung, Ching-Han Huang, Yu-Hsuan Tsai
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Patent number: 11081413Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.Type: GrantFiled: February 21, 2019Date of Patent: August 3, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsin Lin Wu, Yu-Hsuan Tsai, Chang Chin Tsai, Lu-Ming Lai, Ching-Han Huang
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Publication number: 20210206628Abstract: A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.Type: ApplicationFiled: January 3, 2020Publication date: July 8, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Hsuan TSAI, Lu-Ming LAI, Chien-Wei FANG, Ching-Han HUANG
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Patent number: 10841679Abstract: A microelectromechanical systems package structure includes a first substrate, a transducer unit, a semiconductor chip and a second substrate. The first substrate defines a through hole. The transducer unit is electrically connected to the first substrate, and includes a base and a membrane. The membrane is located between the through hole and the base. The semiconductor chip is electrically connected to the first substrate and the transducer unit. The second substrate is attached to the first substrate and defines a cavity. The transducer unit and the chip are disposed in the cavity, and the second substrate is electrically connected to the transducer unit and the semiconductor chip through the first substrate.Type: GrantFiled: January 24, 2018Date of Patent: November 17, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Liang Hsiao, Yu-Hsuan Tsai, Pu Shan Huang, Ching-Han Huang, Lu-Ming Lai
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Patent number: 10804413Abstract: A package component includes a base layer, a sensing layer, a photo-curable adhesive, a cover layer and a first filter structure. The photo-curable adhesive and the sensing layer are disposed on the base layer. The sensing layer includes a sensing unit surrounded by the photo-curable adhesive. The cover layer is disposed on the sensing layer. The first filter structure faces the photo-curable adhesive and is disposed on the cover layer. The first filter structure is configured for transmitting a curing light which is used to cure the photo-curable adhesive, and for reflecting a detectable light which is to be sensed by the sensing unit, where the wavelength of the curing light is different from the wavelength of the detectable light.Type: GrantFiled: December 30, 2019Date of Patent: October 13, 2020Assignee: KINGPAK TECHNOLOGY INCInventor: Yu-Hsuan Tsai
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Publication number: 20200283288Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.Type: ApplicationFiled: May 27, 2020Publication date: September 10, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ming Yen LEE, Chia-Hao SUNG, Ching-Han HUANG, Yu-Hsuan TSAI
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Patent number: 10734337Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.Type: GrantFiled: March 5, 2019Date of Patent: August 4, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kuang-Hsiung Chen, Yu-Hsuan Tsai, Yu-Ying Lee, Sheng-Ming Wang, Wun-Jheng Syu
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Patent number: 10720751Abstract: An optical package structure includes a substrate having a first surface, an interposer bonded to the first surface through a bonding layer, the interposer having a first area from a top view perspective, and an optical device on the interposer, having a second area from the top view perspective, the first area being greater than the second area. A method for manufacturing the optical package structure is also provided.Type: GrantFiled: August 30, 2018Date of Patent: July 21, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Hsuan Tsai, Lu-Ming Lai, Ying-Chung Chen, Shih-Chieh Tang
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Publication number: 20200206735Abstract: A detection method for enhancing detection signal intensity is provided. The detection method includes the following steps. Firstly, a detection device is provided. The detection device includes a channel, an inlet port and an air chamber. The air chamber includes an elastic layer. A bonding material is immobilized in the channel and served as a reaction area. Then, a sample containing a detection material is loaded into the inlet port. As the elastic layer is moved upwardly and downwardly, the sample is moved toward the air chamber and the inlet port in a reciprocating manner. Consequently, the possibility of combining the detection material of the sample with the bonding material in the reaction area is increased. Afterwards, an optical signal from the reaction area is measured.Type: ApplicationFiled: December 10, 2019Publication date: July 2, 2020Inventors: Chi-Han Chiou, Shu-Hsien Liao, Yu-Hsuan Tsai, Ching-Yu Chang