Abstract: A method of processing component carriers is disclosed. The method includes providing a plurality of arrays each comprising a plurality of component carriers, providing a plurality of separator bodies, forming an alternating stack of the arrays and the separator bodies so that each adjacent pair of stacked arrays is spaced by a respective separator body, and carrying out at least one process, in particular at least one back-end process, using the stack. A separator sheet for spacing arrays and a method of using separator sheets for spacing arrays during processing the arrays are also provided.

Abstract: A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.

Abstract: A component carrier includes a base structure with component carrier material and forming a cavity, a component embedded in the cavity, a first electrically insulating layer structure connected to a front side of the base structure and to the component and at least partially filling a gap between the component and the base structure, and a second electrically insulating layer structure connected to the first electrically insulating layer structure at a connection surface of the first electrically insulating layer structure. The connection surface opposes an opposing surface of the second electrically insulating layer structure faces away from the first electrically insulating layer structure.

Abstract: A method of processing component carriers is disclosed. The method includes providing a plurality of arrays each comprising a plurality of component carriers, providing a plurality of separator bodies, forming an alternating stack of the arrays and the separator bodies so that each adjacent pair of stacked arrays is spaced by a respective separator body, and carrying out at least one process, in particular at least one back-end process, using the stack. A separator sheet for spacing arrays and a method of using separator sheets for spacing arrays during processing the arrays are also provided.

Abstract: A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.

Abstract: A method of manufacturing first and second component carriers includes: i) providing a separation component comprising a first separation surface and a second separation surface being opposed to the first separation surface, ii) coupling a first base structure having a first cavity with the first separation surface, iii) coupling a second base structure having a second cavity with the second separation surface, iv) placing a first electronic component in the first cavity, v) connecting the first base structure with the first electronic component to form the first component carrier, vi) placing a second electronic component in the second cavity, vii) connecting the second base structure with the second electronic component to form the second component carrier, viii) separating the first component carrier from the first separation surface of the separation component, and ix) separating the second component carrier from the second separation surface of the separation component.

Abstract: A component carrier includes a base structure with component carrier material and forming a cavity, a component embedded in the cavity, a first electrically insulating layer structure connected to a front side of the base structure and to the component and at least partially filling a gap between the component and the base structure, and a second electrically insulating layer structure connected to the first electrically insulating layer structure at a connection surface of the first electrically insulating layer structure. The connection surface opposes an opposing surface of the second electrically insulating layer structure faces away from the first electrically insulating layer structure.

Abstract: A solder joint with a multilayer IMC structure is provided. The solder joint includes a Cu pad, a Sn-based solder, a first, a second, and a third IMC layer. The Cu pad is disposed opposite to the Sn-based solder. The first IMC layer is disposed between the Cu pad and the Sn-based solder. The first IMC layer is a Cu3Sn layer. The second IMC layer is disposed between the first IMC layer and the Sn-based solder. The second IMC layer is a (Cu1-x1-y1Nix1Pdy1)6Sn5 layer, wherein x1 is in the range between 0 and 0.15, and y1 is in the range between 0 and 0.02. The third IMC layer is disposed between the second IMC layer and the Sn-based solder. The third IMC layer is a (Cu1-x2-y2Nix2Pdy2)6Sn5 layer, wherein x2 is in the range between 0 and 0.4, y2 is in the range between 0 and 0.02, and x2>x1.

Abstract: A chip board package structure includes a circuit board part, a chip board part and a solder used to solder the circuit board part and the chip board part. A chip on the chip board part is connected to an electrical circuit by wiring or soldering. A surface treatment metal layer includes at least nickel, palladium and gold formed on part of the surface of the circuit layer on the chip board. A copper-tin intermetallic compound is formed on joints of the second solder and the surface treatment metal layer, and the other part of the circuit layer is directly connected to the solder to form the copper-tin intermetallic compound. In addition to the lower package cost, with the shape feature of the copper-tin intermetallic compound, it is possible to increase the contact area with the solder, thereby improving the reliability of the soldering process and the yield.

Abstract: A circuit board structure for high frequency signals includes a substrate and an electrical conductive circuit layer formed on the substrate. The conductive circuit layer includes circuit patterns and connection pads. The circuit pattern includes a base part with a shape of a rectangular block and a circular top part with a hemispherical shape provided on the base part. The circular top part can be modified by a circular bottom part embedded in the dielectric plastic film. Alternatively, a double layer structure with the circular top and bottom parts is formed such that the surface of the circuit pattern is provided with hemispheres to strengthen the reflection, thereby overcoming the problem of signal concentration due to the rectangular structure or the issue of signal attenuation due to surface roughness.

Abstract: A system and method for using an encoding module in a virtual world server for: receiving scene data including a description of at least one virtual object and underlying terrain associated with the scene; organizing the description of the at least one virtual object into a first track segmented by virtual object time slots, organizing the description of the underlying terrain into a second track segmented by terrain time slots; and storing the descriptions in persistent storage as separate files where users can retrieve and render the separate files.

Abstract: A solder joint with a multilayer IMC structure is provided. The solder joint includes a Cu pad, a Sn-based solder, a first, a second, and a third IMC layer. The Cu pad is disposed opposite to the Sn-based solder. The first IMC layer is disposed between the Cu pad and the Sn-based solder. The first IMC layer is a Cu3Sn layer. The second IMC layer is disposed between the first IMC layer and the Sn-based solder. The second IMC layer is a (Cu1-x1-y1Nix1Pdy1)6Sn5 layer, wherein x1 is in the range between 0 and 0.15, and y1 is in the range between 0 and 0.02. The third IMC layer is disposed between the second IMC layer and the Sn-based solder. The third IMC layer is a (Cu1-x2-y2Nix2Pdy2)6Sn5 layer, wherein x2 is in the range between 0 and 0.4, y2 is in the range between 0 and 0.02, and x2>x1.

Abstract: A surface treatment structure formed on a circuit pattern on a printed circuit board is provided, which includes a first gold layer, a palladium layer, and a second gold layer stacked from bottom to top, respectively, or includes a palladium layer, and a second gold layer stacked from bottom to top, respectively. The palladium layer is used to prevent the diffusion of the copper ions from the circuit pattern. Only a thin surface treatment structure of the circuit pattern of the present invention is required to achieve excellent wire bonding, so that the overall thickness is reduced, and the manufacture cost is also reduced. Furthermore, the uniformness of palladium is better than that of nickel, and thereby the surface treatment structure of the circuit pattern of the present invention is suitably used for manufacturing the fine-line circuits, thereby having a wider industrial applicability.

Abstract: A system and method for using an encoding module in a virtual world server for: receiving scene data including a description of at least one virtual object and underlying terrain associated with the scene; organizing the description of the at least one virtual object into a first track segmented by virtual object time slots, organizing the description of the underlying terrain into a second track segmented by terrain time slots; and storing the descriptions in persistent storage as separate files where users can retrieve and render the separate files.