Patents by Inventor Yu-Jen Kuo

Yu-Jen Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996400
    Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. Top packages are mounted on a top side of a reconstructed wafer over a flexible tape, where conductive bumps at a bottom side of the reconstructed wafer is attached to the flexible tape, and during the mounting, a shape geometry of the respective conductive bump changes and at least a lower portion of the respective conductive bump is embraced by the flexible tape. The flexible tape is released from the conductive bumps after the mounting.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-Shuan Chung
  • Publication number: 20240132621
    Abstract: Disclosed herein an isolated neutralizing antibody, which is capable of specifically binding to chitinase-3-like protein-1 (YKL-40) and uses thereof. The neutralizing antibody can further conjugate with a metal chelator to form an antibody complex. Further, labeling the antibody complex with a radioactive metal nuclide results in formation of a radioactive antibody complex, which can be used as a contrast agent and treatment for YKL-40 over-expression-related diseases. The radioactive antibody complex can specifically bind to YKL-40, and can be used for diagnosis and the preparation of the use of the treatment for cancers related to YKL-40 over-expression.
    Type: Application
    Filed: April 18, 2023
    Publication date: April 25, 2024
    Inventors: Ming-Cheng Chang, Ping-Fang Chiang, Yu-Jen Kuo
  • Patent number: 11961810
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 11942451
    Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
  • Patent number: 6364713
    Abstract: An electrical connector adapter assembly (40) comprises a first dielectric housing (51), three sets of first terminals (52), (53), (54) retained in the first dielectric housing (51), a printed circuit board (PCB) (70), a set of conductors (80), a second dielectric housing (61) and two sets of second terminals (62) retained in the second dielectric housing (61). The PCB (70) has two sets of first circuit pads (71) and two sets of second circuit pads (72) in an upper and a lower surfaces (74), (75) thereof and a number of conductive devices (76) in the upper surface (74). Each conductor (80) has a first end (81) and a second end (82) electrically connecting a corresponding one of the uppermost set of first terminals (52) and a corresponding one of the conductive devices (76) of the PCB, respectively.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: April 2, 2002
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventor: Yu Jen Kuo
  • Patent number: 6343957
    Abstract: A DVI electrical adapter (2) for electrically connecting a monitor to a host computer having different interfaces includes a combined digital & analog receptacle connector (21), a digital-only plug connector (22), two printed circuit boards (PCBs) (23) joined between the plug connector and the receptacle connector, an insulative housing (20) insert molded over a center of the DVI adapter and a pair of elongated fasteners (24). The elongated fasteners project through two sides of the insulative housing and include a first fixing end (241) and a second fixing end (243). The second fixing end engages with nuts of a complementary receptacle connector mounted on the host computer. The first fixing end has a threaded recess accepting screws from a cable plug connector attached to the monitor. The DVI electrical adapter has a smaller size and simpler structure, and is simpler to use than prior art DVI connector.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: February 5, 2002
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Yu-Jen Kuo, Chin-Pao Kuo
  • Patent number: 6340314
    Abstract: An electrical adapter (3) includes a first connector (1) having a number of terminals (10), a second connector (2) having a number of pins (20), and an insulating shell member (30) covering a junction portion where the first connector and the second connector are interconnected. Each terminal or pin has a contacting portion (140, 240) for mating with a contact of a complementary connector and a soldering portion (142, 242). Selected sddering portions of the terminals and the pins are soldered with each other to make respective electrical connections. Some of the terminals or the pins are curved for being soldered directly with corresponding terminals or pins in accordance with the need of desired signal transmission, thereby achieving a cost-effective and easy-processing adapter.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: January 22, 2002
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventor: Yu-Jen Kuo