Patents by Inventor Yu-Jen Wang

Yu-Jen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230217834
    Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.
    Type: Application
    Filed: March 10, 2023
    Publication date: July 6, 2023
    Inventors: Vignesh Sundar, Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Sahil Patel, Yu-Jen Wang, Tom Zhong
  • Publication number: 20230213808
    Abstract: An optical system includes a pancake lens assembly and a varifocal lens device. The varifocal lens device is coupled to the pancake lens assembly in a way that an optical axis of the varifocal lens device is in alignment with an optical axis of the pancake lens assembly, thereby permitting the optical system to have an adjustable focal length.
    Type: Application
    Filed: May 16, 2022
    Publication date: July 6, 2023
    Inventors: Yi-Hsin Lin, Ting-Wei Huang, Yu-Jen Wang
  • Patent number: 11696511
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sahil Patel, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Dongna Shen, Yu-Jen Wang, Po-Kang Wang, Huanlong Liu
  • Publication number: 20230196558
    Abstract: A medicine image recognition method applied to an electronic device is provided. The method includes obtaining target images by inputting medicine images into a position detection network. Character feature matrices are generated according to the target images and a character recognition network. Image feature matrices are generated by inputting the target images into a category recognition network. Reference matrices are generated according to the image feature matrices and corresponding character feature matrices. Once a matrix to be tested is generated by processing an image to be tested, and a recognition result of the image to be tested is generated according to a similarity between the matrix to be tested and each of the reference matrices.
    Type: Application
    Filed: June 20, 2022
    Publication date: June 22, 2023
    Inventors: YU-JEN WANG, MENG-PING LU
  • Patent number: 11669046
    Abstract: A display device includes a light source, a waveguide element, a liquid crystal coupler, a first holographic optical element and a second holographic optical element. The light source is configured to emit light. The waveguide element is located above the light source. The liquid crystal coupler is located between the waveguide element and the light source. The first holographic optical element is located on a top surface of the waveguide element, in which the liquid crystal coupler is configured to change an incident angle that the light emits to the first holographic optical element. The second holographic optical element is located on the top surface of the waveguide element, and there is a first distance in a horizontal direction between the first holographic optical element and the second holographic optical element, in which the second holographic optical element is configured to diffract the light to the waveguide element below.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: June 6, 2023
    Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (SingZhen) Co., Ltd., Interface Optoelectronics (Wuxi) Co., Ltd., General Interface Solution Limited
    Inventors: Shih-Yu Wang, Chun-Ta Chen, Shiuan-Huei Lin, Zih-Fan Chen, Wan-Lin Li, Yi-Hsin Lin, Yu-Jen Wang, Wei-Cheng Cheng, Chang-Nien Mao
  • Publication number: 20230122971
    Abstract: A force sensing device is mounted on a tool to sense force, particularly quasi-static and static forces. The force sensing device includes at least one a sensor. A piezoelectric element in the sensor includes a driving portion and a sensing portion. A first voltage is input to the driving portion to generate a vibration in the piezoelectric element and a second voltage in response to the vibration is output from the sensing portion. The second voltage output from the sensing portion is changed as the vibration in the piezoelectric element is suppressed by an external force acting on the force sensing device so variation of the second voltage can be used to measure the external force.
    Type: Application
    Filed: December 14, 2021
    Publication date: April 20, 2023
    Inventors: Yu-Jen Wang, Yu-Jan Lo, Ren-Yi Huang
  • Patent number: 11631802
    Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 18, 2023
    Assignee: Headway Technologies, Inc.
    Inventors: Vignesh Sundar, Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Sahil Patel, Yu-Jen Wang, Tom Zhong
  • Patent number: 11597993
    Abstract: A MgO layer is formed using a process flow wherein a Mg layer is deposited at a temperature <200° C. on a substrate, and then an anneal between 200° C. and 900° C., and preferably from 200° C. and 400° C., is performed so that a Mg vapor pressure >10?6 Torr is reached and a substantial portion of the Mg layer sublimes and leaves a Mg monolayer. After an oxidation between ?223° C. and 900° C., a MgO monolayer is produced where the Mg:O ratio is exactly 1:1 thereby avoiding underoxidized or overoxidized states associated with film defects. The process flow may be repeated one or more times to yield a desired thickness and resistance×area value when the MgO is a tunnel barrier or Hk enhancing layer. Moreover, a doping element (M) may be added during Mg deposition to modify the conductivity and band structure in the resulting MgMO layer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sahil Patel, Guenole Jan, Yu-Jen Wang
  • Publication number: 20230060687
    Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance×area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.
    Type: Application
    Filed: November 7, 2022
    Publication date: March 2, 2023
    Inventors: Vignesh Sundar, Yu-Jen Wang, Luc Thomas, Guenole Jan
  • Patent number: 11563171
    Abstract: A magnetic tunneling junction (MTJ) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same the second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Publication number: 20230004015
    Abstract: An optical system includes a pancake lens assembly which has a lens unit and a liquid crystal device. The lens unit includes a partially reflective mirror, a reflective polarizer, and a quarter waveplate disposed between the partially reflective mirror and the reflective polarizer. The liquid crystal device is disposed between the quarter waveplate and the reflective polarizer. When a light is introduced into the pancake lens assembly in a Z direction, an X-polarized light passes through the liquid crystal device two times and a Y-polarized light passes through the liquid crystal device one time.
    Type: Application
    Filed: February 9, 2022
    Publication date: January 5, 2023
    Applicant: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Yu-Jen WANG, Yi-Hsin LIN
  • Patent number: 11545622
    Abstract: An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60 nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Zhongjian Teng, Yu-Jen Wang
  • Publication number: 20220415504
    Abstract: A method training an AI model in disease identification establishes a disease identifying model, the model includes a convolutional neural network and a pyramid attention network. The pyramid attention network receives output of the convolutional neural network. The method obtains feature map sample set, the sample set being classified into training sets and verification sets. The method inputs each training set into the disease identifying model to train the model and outputs values of degree of confidence in correct identification of diseases. The method further verifies the trained models according to the verification sets. An electronic device and a non-transitory storage medium are also disclosed.
    Type: Application
    Filed: November 30, 2021
    Publication date: December 29, 2022
    Inventor: YU-JEN WANG
  • Patent number: 11520181
    Abstract: A flexible optical element adopting liquid crystals (LCs) as the materials for realizing electrically tunable optics is foldable. A method for manufacturing the flexible element includes patterned photo-polymerization. The LC optics can include a pair of LC layers with orthogonally aligned LC directors for polarizer-free properties, flexible polymeric alignment layers, flexible substrates, and a module for controlling the electric field. The lens power of the LC optics can be changed by controlling the distribution of electric field across the optical zone. Lens power control can be provided using combinations of electrode configurations, drive signals and anchoring strengths in the alignment layers.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: December 6, 2022
    Assignee: COOPERVISION INTERNATIONAL LIMITED
    Inventors: Hung-Chun Lin, Yu-Jen Wang, Hao-Ren Lo, Yi-Hsin Lin
  • Publication number: 20220384718
    Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 1, 2022
    Inventors: Vignesh Sundar, Yu-Jen Wang, Dongna Shen, Sahil Patel, Ru-Ying Tong
  • Patent number: 11504551
    Abstract: A system for adjusting radiation target sites dynamically according to the moving states of a target object and for creating a lookup table of the moving states includes a detection chip, a radiation generation device, and a lookup table. The detection chip can be fixed on the target object to detect the current moving state of the target object. The detection chip or the radiation generation device, both configured for wireless signal transmission to each other, can activate or deactivate the radiation emitters of the radiation generation device individually according to the current moving state of the target object and the contents of the lookup table. As the system uses wireless transmission, and the lookup table has recorded the working state of each radiation emitter in each moving state of the target object, radiotherapy can be performed without a large number of tubes or sensors.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: November 22, 2022
    Inventors: Jian-Kuen Wu, Yu-Jen Wang
  • Publication number: 20220367792
    Abstract: A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Publication number: 20220367793
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Yi YANG, Dongna SHEN, Vignesh SUNDAR, Yu-Jen WANG
  • Publication number: 20220359821
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
  • Patent number: 11495738
    Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance×area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Vignesh Sundar, Yu-Jen Wang, Luc Thomas, Guenole Jan