Abstract: A display device includes a display panel having a general area including first subpixels, and a sensor area including second subpixels and light-transmitting area. Each of the first subpixels and the second subpixels includes a first active layer disposed on a substrate and formed of a first material, a first gate layer disposed on the first active layer, a second gate layer disposed on the first gate layer, a second active layer disposed on the second gate layer and formed of a second material different from the first material, a third gate layer disposed on the second active layer, and a light-blocking layer disposed between the substrate and the first active layer and overlapping the second active layer in a thickness direction.

Abstract: Disclosed is an image sensing device including a first clock distributor suitable for receiving a first input clock signal through a first input terminal, and outputting a plurality of first output clock signals through a plurality of first output terminals, and a first conductive line coupled in common to the plurality of first output terminals.

Abstract: An image sensing device includes: a control circuit coupled between an output terminal of a pixel signal and a high voltage terminal, and configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supplying circuit coupled between the output terminal and the high voltage terminal, and configured to supply a pre-charge current, which is configured to be adaptively adjusted according to the voltage level of the pixel signal, to the output terminal based on the control voltage.

Abstract: A display device includes: a substrate; a light emitting element layer disposed on the substrate; and a sensor electrode layer disposed on an encapsulation layer and including: a plurality of first touch electrode groups extending along a first direction; a plurality of first touch electrodes, of the plurality of first touch electrode groups, arranged along the first direction; a plurality of second touch electrode groups extending along the second direction and arranged along the first direction; a first contact electrode connected to any one of the plurality of first touch electrodes of any one of the plurality of first touch electrode groups; and a second contact electrode connected to any one of the plurality of first touch electrodes of another of the plurality of first touch electrode groups, and wherein an area of the first contact electrode is greater than an area of the second contact electrode.

Abstract: Disclosed is an image sensing device including a first clock distributor suitable for receiving a first input dock signal through a first input terminal, and outputting a plurality of first output clock signals through a plurality of first output terminals, and a first conductive line coupled in common to the plurality of first output terminals.

Abstract: An embodiment resin composition for shielding electromagnetic waves, based on a total weight of the resin composition, includes 20 to 80 wt % of thermoplastic resin, 1 to 50 wt % of a conductive filler, and 0.1 to 30 wt % of an additive.

Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

Abstract: The present specification relates to a compound as a UBR box domain ligand. The present specification provides a small molecule compound that binds to the UBR box domain. Further, the present specification provides a composition for inhibiting UBR box domain substrate binding, including a ligand compound that binds to a UBR box domain, a pharmaceutical composition for treating UBR-related disease, and a use thereof.

Abstract: The present specification relates to a compound as a UBR box domain ligand. The present specification provides a small molecule compound that binds to the UBR box domain. Further, the present specification provides a composition for inhibiting UBR box domain substrate binding, including a ligand compound that binds to a UBR box domain, a pharmaceutical composition for treating UBR-related disease, and a use thereof.

Abstract: A multiplex PCR chip capable of simultaneously detecting multiple target genes and a multiplex PCR method using the same are proposed. More specifically, in the multiplex PCR chip and multiplex PCR method, after a plurality of spatially separated particle-forming grooves is formed in one or more reaction chambers and a probe in a solution state is injected into the particle-forming grooves, planar shapes of the particle-forming grooves are varied or shapes and patterns of particle holders respectively formed on inner surfaces of the particle-forming grooves are varied, and the probe including primers specifically hybridizing with sequences of different nucleic acid molecules is injected into the particle-forming grooves, whereby simultaneous multiplex detection is possible by allowing multiple target genes to be detected on the basis of positions and shapes of the probe particles and the shapes and patterns of the particle holders respectively formed inside of the probe particles.

Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.

Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.