Patents by Inventor Yu-Jui Chen
Yu-Jui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178197Abstract: A micro LED display device and manufacturing method thereof. The micro LED display device includes a circuit substrate, a pixel structure layer, a support structure, a connection layer and a protection layer. The pixel structure layer is disposed on the top surface of the circuit substrate, and has plural micro LED units disposed separately. The micro LED units face the top surface and are electrically connected with the circuit substrate. The support structure is disposed on the top surface, extending from the top surface to the pixel structure layer and connected with the side surface of the pixel structure layer. The support structure protrudes from a surface of the pixel structure layer away from the circuit substrate. The connection layer is disposed in the accommodating space formed by the support structure and the surface of the pixel structure layer. The protection layer is disposed on the connection layer.Type: ApplicationFiled: December 21, 2022Publication date: May 30, 2024Inventors: YEN-YEH CHEN, YU-JUI TSENG
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Publication number: 20240168050Abstract: A shock indicator, including a first cover, a base, a counterweight, and a shrapnel, is provided. The first cover has an accommodating space. The base is disposed in the accommodating space of the first cover. The counterweight is located in the accommodating space. The counterweight has a pivot end pivotally disposed on the base, and the counterweight rotates relative to the base with the pivot end as a rotation axis. The shrapnel is disposed on the base and is located in the accommodating space. The counterweight and the shrapnel are located on two opposite sides of the base. The shrapnel has two ends, and the two ends of the shrapnel clamp the counterweight along a contour of the counterweight.Type: ApplicationFiled: August 20, 2023Publication date: May 23, 2024Applicant: Industrial Technology Research InstituteInventors: Yu-Jan Lo, Shih-Jia Shen, Sheng-Jui Chen
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Publication number: 20240160844Abstract: The present disclosure provides a synonym searching method, which includes steps as follows. When receiving the vocabulary and the definition of the vocabulary from the user device, the natural language processing model is used to search the synonym of the vocabulary from the data governance dictionary according to the definition of the vocabulary; after providing the synonym to the user device, feedback information about the synonym is received from the user device, and the feedback information is used as the token of the vocabulary for the natural language processing model.Type: ApplicationFiled: February 8, 2023Publication date: May 16, 2024Inventors: Wei-Chao CHEN, Chen-I HUANG, Yu-Lun CHANG, Chuo-Jui WU, Chih-Pin WEI
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Publication number: 20240150906Abstract: An electrolytic cell includes a cation exchange membrane, a cathode compartment, and an anode compartment. The cathode compartment includes a gas diffusion electrode and a flow channel element, in which the flow channel element is between the cation exchange membrane and the gas diffusion electrode, and has a plurality of flow channels arranged in parallel with each other. The anode compartment includes an anode mesh, in which the cation exchange membrane is between the anode mesh and the flow channel element. A distance between the anode mesh and the gas diffusion electrode is substantially equal to the sum of a first thickness of the cation exchange membrane and a second thickness of the flow channel element. The novel electrolytic cell can combine with a chloralkali electrolytic cell to deal with gaseous CO2 and produce products, e.g., synthesis gas, for other purposes.Type: ApplicationFiled: May 9, 2023Publication date: May 9, 2024Inventors: Hao-Ming CHEN, Tai-Lung CHEN, Wan-Tun HUNG, Yu-Cheng CHEN, Kuo-Ming HUANG, Fu-Da YEN, Che-Jui LIAO
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Publication number: 20240136420Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.Type: ApplicationFiled: December 1, 2022Publication date: April 25, 2024Applicant: AUO CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
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Publication number: 20240128626Abstract: A transmission device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.Type: ApplicationFiled: November 25, 2022Publication date: April 18, 2024Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan UniversityInventors: Yu-Kuang WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
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Package structure comprising buffer layer for reducing thermal stress and method of forming the same
Patent number: 11961777Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.Type: GrantFiled: June 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao -
Patent number: 11955507Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
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Patent number: 11948863Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.Type: GrantFiled: February 8, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
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Patent number: 11948904Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.Type: GrantFiled: March 21, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Patent number: 11192778Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.Type: GrantFiled: July 13, 2020Date of Patent: December 7, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Patent number: 11163773Abstract: Disclosed herein are system, method, and computer program product embodiments for partition pruning using globally encoded range partition information. An embodiment operates by partitioning a data table into a plurality of data partitions, determining a plurality of sub-partitions within the data partitions, and determining a global range table based at least in part on value ranges corresponding to the sub-partitions. Further, the global range table may be used to determine bit vectors for the data partitions and query predicates. In some examples, the bit vectors may be used to determine whether to prune data partitions during execution of a query over a large data volume.Type: GrantFiled: April 27, 2018Date of Patent: November 2, 2021Assignee: SAP SEInventors: Yu-Jui Chen, Reza Sherkat, John Smirnios, Mihnea Andrei
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Publication number: 20200339413Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventors: Yu-Jui CHEN, I-Shi WANG, Ren-Dou LEE, Jen-Hao LIU
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Patent number: 10759654Abstract: The present disclosure relates to a method for manufacturing a microelectromechanical systems (MEMS) package. The method comprises providing a CMOS IC including CMOS devices arranged within a CMOS substrate. The method further comprises forming and patterning a metal layer over the CMOS substrate to form an anti-stiction layer and a fixed electrode plate and forming a rough top surface for the anti-stiction layer. The method further comprises providing a MEMS IC comprising a moveable mass arranged within a recess of a MEMS substrate and bonding the CMOS IC to the MEMS IC to enclose a cavity between the moveable mass and the fixed electrode plate and the anti-stiction layer.Type: GrantFiled: December 21, 2018Date of Patent: September 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Patent number: 10710872Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.Type: GrantFiled: December 6, 2017Date of Patent: July 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Publication number: 20200095532Abstract: A fermentation monitoring device is provided for monitoring a fermentation process in a bottle, and includes a detecting unit disposed at a cap body for continuously monitoring at least one environment parameter in the bottle; a weight scale disposed for detecting a weight of contents in the bottle; and a processor that, in response to receipt of an activation signal, is configured to calculate an estimated time to completion of the fermentation process, generate an alert response when a value of the environment parameter is out of a corresponding predetermined range, and determine whether the fermentation process has completed and generate a completion signal when it has.Type: ApplicationFiled: November 27, 2019Publication date: March 26, 2020Inventors: Tsan-Hao YANG, Ching-Yen CHANG, Yu-Jui CHEN, Yu-Wen HUANG
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Publication number: 20190236193Abstract: Disclosed herein are system, method, and computer program product embodiments for partition pruning using globally encoded range partition information. An embodiment operates by partitioning a data table into a plurality of data partitions, determining a plurality of sub-partitions within the data partitions, and determining a global range table based at least in part on value ranges corresponding to the sub-partitions. Further, the global range table may be used to determine bit vectors for the data partitions and query predicates. In some examples, the bit vectors may be used to determine whether to prune data partitions during execution of a query over a large data volume.Type: ApplicationFiled: April 27, 2018Publication date: August 1, 2019Inventors: Yu-Jui CHEN, Reza Sherkat, John Smirnios, Mihnea Andrei
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Publication number: 20190119099Abstract: The present disclosure relates to a method for manufacturing a microelectromechanical systems (MEMS) package. The method comprises providing a CMOS IC including CMOS devices arranged within a CMOS substrate. The method further comprises forming and patterning a metal layer over the CMOS substrate to form an anti-stiction layer and a fixed electrode plate and forming a rough top surface for the anti-stiction layer. The method further comprises providing a MEMS IC comprising a moveable mass arranged within a recess of a MEMS substrate and bonding the CMOS IC to the MEMS IC to enclose a cavity between the moveable mass and the fixed electrode plate and the anti-stiction layer.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Patent number: 10173886Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC and a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.Type: GrantFiled: January 31, 2018Date of Patent: January 8, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Publication number: 20180179047Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC and a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.Type: ApplicationFiled: January 31, 2018Publication date: June 28, 2018Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu