Patents by Inventor Yu-Jung Lo

Yu-Jung Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959956
    Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 6077098
    Abstract: An electrical connector has a first insulative housing including an elongate bridging portion from two ends of which two guiding arms extend for guiding a memory card toward the bridging portion. The guiding arms each have a first engaging portion confronting each other. A second elongate insulative housing is detachably assembled to the first housing between the guiding arms thereof. The second housing defines a plurality of passageways for receiving contacts therein and has a second engaging portion at each end thereof for detachably engaging with the first engaging portion of the first housing. The detachable second housing allows replacement of contacts therein for adjusting to different capacities of memory modules.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: June 20, 2000
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Kuo-Hsiao Yu, Yu-Jung Lo
  • Patent number: D403315
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: December 29, 1998
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Richard C. Y. Fu, Jason Ji, Yu-Jung Lo
  • Patent number: D403316
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: December 29, 1998
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Richard C. Y. Fu, Jason Ji, Yu Jung Lo