Abstract: A liquid-repellent structure includes a surface to which liquid repellency is to be imparted; a foundation layer having a surface and disposed to face the surface to which liquid repellency is to be imparted; and a liquid-repellent layer disposed to face the surface of the foundation layer, wherein the foundation layer contains an acid-modified polyolefin, the liquid-repellent layer contains a fluorine-containing resin and particles, and the fluorine-containing resin contains a hydrophilic structural unit having at least one of an amino group and an amide group. A packaging material has the liquid-repellent structure disposed to face a product. The packaging material can also be applied to a product that is a selected one of hand soap, body soap, shampoo, rinse, creams, and cosmetics and that contains a surfactant.

Abstract: An external control FPGA device includes a command receiving terminal configured to receive command data, a control outputting terminal configured to output a functioning control signal, and a plurality of FPGA connection terminals, and a data processing FPGA device that transmits a control command from an external command data receiver to a control signal outputter. The data processing FPGA device is connected to one of the plurality of FPGA connection terminals through a data processing line that is independent of a command transmission pathway including an external command data receiver, a command data line, the external control FPGA device, a functioning control signal line and the control signal outputter. The data processing FPGA device inputs data that is to be processed from the external control FPGA device through the data processing line, and outputs the processed data to the external control FPGA device.

Abstract: A controller for providing a DRP port according to USB Type-C standard. A state manager coupled to a power manager for controlling charging and discharging of a battery. A signal transmission module for exchanging a signal with a connection destination via a communication line in the USB cable according to an instruction from the state manager. The signal transmission module is possible to indicate the communication line whether the port is featured as the power supply side or the power reception side. When the port is featured as the power supply side, the state manager supplies an electric power stored in the battery to the connection destination and if the battery becomes the condition of Low Battery, the state manager stops supplying the electric power to the connection destination while maintaining the state that the port is featured as the power supply side.

Abstract: A controller for providing a DRP port according to USB Type-C standard. A state manager coupled to a power manager for controlling charging and discharging of a battery. A signal transmission module for exchanging a signal with a connection destination via a communication line in the USB cable according to an instruction from the state manager. The signal transmission module is possible to indicate the communication line whether the port is featured as the power supply side or the power reception side. When the port is featured as the power supply side, the state manager supplies an electric power stored in the battery to the connection destination and if the battery becomes the condition of Low Battery, the state manager stops supplying the electric power to the connection destination while maintaining the state that the port is featured as the power supply side.

Abstract: A high-frequency integrator acquires a first integrated value by integrating a high-frequency component of first image data. A corrector handles second image data, which is obtained when an image processor subjects the first image data to an image process affecting frequency characteristics, and acquires a second integrated value by correcting the first integrated value acquired by the high-frequency integrator in accordance with a change in the frequency characteristics that is brought about by the image process. An encoder calculates, in accordance with the second integrated value acquired by the corrector, a quantization scale for compressing the second image data acquired by the image processor to a predefined number of bytes at once, and compresses the second image data accordingly.

Abstract: A high-frequency integrator acquires a first integrated value by integrating a high-frequency component of first image data. A corrector handles second image data, which is obtained when an image processor subjects the first image data to an image process affecting frequency characteristics, and acquires a second integrated value by correcting the first integrated value acquired by the high-frequency integrator in accordance with a change in the frequency characteristics that is brought about by the image process. An encoder calculates, in accordance with the second integrated value acquired by the corrector, a quantization scale for compressing the second image data acquired by the image processor to a predefined number of bytes at once, and compresses the second image data accordingly.