Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE initiates a mobile originated (MO) procedure for modifying an Evolved Packet System (EPS) bearer to release all traffic flows associated with the EPS bearer. The UE receives a request to initiate a mobile terminated (MT) procedure for modifying the EPS bearer. The UE, in response to receiving the request, aborts the MO procedure. The UE locally deactivates the EPS bearer.

Abstract: A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.

Abstract: The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A signal processing transformation (wavelet, Fourier, discrete cosine) is applied to a digital image on a mobile device in order to produce a low-level information image and at least one high-level information image. The low-level image is recognizable as the digital image and is kept on the device; all other related images are deleted. The high-level information images are uploaded. The transformation is applied recursively and is dictated by a default setting, calculated from data of the mobile device, or input. To regenerate the original image the device connects to the server and downloads a set of high-level information images or all sets. The low resolution image is combined with the high-level information images using the reverse of the transformation originally applied to produce a higher resolution version of the low resolution image. Successive sets of high-level information images may be recursively applied to generate successively higher resolution images.