Patents by Inventor Yu-Li Tsai

Yu-Li Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11974311
    Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The method includes receiving, from a base station (BS), a Radio Resource Control (RRC) configuration to configure a first semi-persistent scheduling (SPS) physical downlink shared channel (PDSCH) and generating first uplink control information (UCI) in response to the first SPS PDSCH, where the RRC configuration includes a first parameter that indicates a priority of the first UCI.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: April 30, 2024
    Assignee: Hannibal IP LLC
    Inventors: Wan-Chen Lin, Yu-Hsin Cheng, Heng-Li Chin, Hsin-Hsi Tsai
  • Publication number: 20240136459
    Abstract: A multi junction solar cell structure includes a first sub-cell, a first tunnel diode layer, a second tunnel diode layer, a second sub-cell, a lattice gradient buffer layer and a third sub-cell. The first sub-cell includes a first surface and a second surface opposite to the first surface. The first tunnel diode layer is formed on the first surface of the first sub-cell. The second sub-cell is formed on the first tunnel diode layer. The second tunnel diode layer is formed on the second surface of the first sub-cell. The lattice gradient buffer layer is formed on the second tunnel diode. The third sub-cell is formed on the lattice gradient buffer layer. This disclosure also contains a method for manufacturing the above-mentioned multi-junction solar cell.
    Type: Application
    Filed: April 19, 2023
    Publication date: April 25, 2024
    Inventors: YU-LI TSAI, Chih-Hung Wu
  • Publication number: 20240088307
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11232950
    Abstract: The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: January 25, 2022
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.O.C.
    Inventors: Jheng Hao Fang, Yu Li Tsai, Hsueh-Hui Yang, Chih Hung Wu, Hwen Fen Hong
  • Publication number: 20200343093
    Abstract: The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.
    Type: Application
    Filed: November 1, 2019
    Publication date: October 29, 2020
    Inventors: JHENG HAO FANG, YU LI TSAI, HSUEH-HUI YANG, CHIH HUNG WU, HWEN FEN HONG
  • Patent number: 10635620
    Abstract: A functional module board for outputting an output signal to an application terminal includes a main board and a sub board. The main board includes a processor and a main board connector. The sub board includes a sub board connector, a signal converter, and a signal output terminal. The main board connector is detachably connected to the sub board connector, and the processor sends a native signal to the sub board. The sub board converts the native signal to the output signal via the signal converter after receiving the native signal, and the signal output terminal outputs the output signal to the application terminal. The functional module board of the present application can change the design of the sub board according to different application terminal requirements in the case of the same main board to save the development cost.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 28, 2020
    Assignee: ADLINK TECHNOLOGY INC.
    Inventors: Yu-Li Tsai, Yu-Yun Liu, Shih-Hsun Chou
  • Publication number: 20190361828
    Abstract: A functional module board for outputting an output signal to an application terminal includes a main board and a sub board. The main board includes a processor and a main board connector. The sub board includes a sub board connector, a signal converter, and a signal output terminal. The main board connector is detachably connected to the sub board connector, and the processor sends a native signal to the sub board. The sub board converts the native signal to the output signal via the signal converter after receiving the native signal, and the signal output terminal outputs the output signal to the application terminal. The functional module board of the present application can change the design of the sub board according to different application terminal requirements in the case of the same main board to save the development cost.
    Type: Application
    Filed: November 9, 2018
    Publication date: November 28, 2019
    Inventors: Yu-Li Tsai, Yu-Yun Liu, Shih-Hsun Chou
  • Patent number: 8575004
    Abstract: The present invention related to a lift-off structure adapted to a substrate having a photoelectric device, the structure comprising: a buffer layer, forming on the substrate; an upper sacrificial layer, forming on the buffer layer; an etch stop layer, forming on the upper sacrificial layer, and the photoelectric device structure forming on the etch stop layer.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 5, 2013
    Assignee: Institute of Nuclear Energy Research Atomic Energy Council, Executive Yuan
    Inventors: Yu-Li Tsai, Chih-Hung Wu, Jei-Li Ho, Chao-Huei Huang, Min-De Yang
  • Patent number: 8497421
    Abstract: A lift-off structure for substrate of a photoelectric device and method thereof, which making it possible to enable an etching solution to flow through not only external etch channel but also internal etch channel to etch a sacrificial layer in order to increase the overall etching speed and decrease the overall time of lifting a substrate off.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 30, 2013
    Assignee: Institute of Nuclear Energy Research Atomic Energy Council, Executive Yuan
    Inventors: Yu-Li Tsai, Chih-Hung Wu, Jei-Li Ho
  • Publication number: 20130048058
    Abstract: A lift-off structure for substrate of a photoelectric device and method thereof, which making it possible to enable an etching solution to flow through not only external etch channel but also internal etch channel to etch a sacrificial layer in order to increase the overall etching speed and decrease the overall time of lifting a substrate off.
    Type: Application
    Filed: September 20, 2011
    Publication date: February 28, 2013
    Applicant: Institute of Nuclear Energy Research Atomic Energy Council, Executive Yuan
    Inventors: YU-LI TSAI, Chih-Hung Wu, Jei-Li Ho
  • Publication number: 20120273815
    Abstract: The present invention related to a lift-off structure adapted to a substrate having a photoelectric device, the structure comprising: a buffer layer, forming on the substrate; an upper sacrificial layer, forming on the buffer layer; an etch stop layer, forming on the upper sacrificial layer, and the photoelectric device structure forming on the etch stop layer.
    Type: Application
    Filed: October 14, 2011
    Publication date: November 1, 2012
    Applicant: Institute of Nuclear Energy Research Atomic Energy Council, Executive Yuan
    Inventors: YU-LI TSAI, Chih-Hung Wu, Jei-Li Ho, Chao-Huei Huang, Min-De Yang
  • Publication number: 20120222739
    Abstract: A photovoltaic apparatus includes a substrate, a light-concentrating heat sink unit and a solar cell. The light-concentrating heat sink unit includes a carrier connected to the substrate, at least two fins extending from the carrier, and at least two reflective layers each extending on a related one of the fins. The solar cell includes a lower electrode and a solder layer of low thermal resistance provided between the lower electrode and the carrier.
    Type: Application
    Filed: March 2, 2011
    Publication date: September 6, 2012
    Applicant: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCH
    Inventors: Yu-Li Tsai, Chih-Hung Wu
  • Publication number: 20120216857
    Abstract: Disclosed is a solar cell assembly with excellent photocurrent collection efficiency. The solar cell assembly includes a solar cell and a surface barrier layer. The solar cell includes a window layer. The surface barrier layer is provided on the window layer. The surface barrier layer is made of phosphide or arsenide.
    Type: Application
    Filed: February 28, 2011
    Publication date: August 30, 2012
    Applicant: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCH
    Inventors: Yu-Li Tsai, Chih-Hung Wu
  • Patent number: 8143590
    Abstract: An ion source apparatus has an ion source assembly and a neutralizer. The ion source assembly has a body, a heat-dissipating device, an anode chunk and a gas distributor. The heat-dissipating device has a thermal transfer plate and a first thermal side sheet. The thermal transfer plate has a top, a protrusion and an annular disrupting recess. The protrusion is formed at the top of the thermal transfer plate. The disrupting recess is radially formed around the protrusion. The first thermal side sheet surrounds the protrusion. The gas distributor is mounted securely in the protrusion. Because the protrusion is located between the gas distributor and the first thermal side sheet and the disrupting recess is radially formed around the protrusion, accumulated ions, molecules and deposition film particles are longitudinally disrupted and do not form a short circuit between the gas distributor and the first thermal side sheet.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: March 27, 2012
    Inventors: Tsai-Cheng Wang, Chin-Chung Yang, An-Ting Hsiao, Yu-Li Tsai
  • Publication number: 20120012755
    Abstract: An ion source apparatus has an ion source assembly and a neutralizer. The ion source assembly has a body, a heat-dissipating device, an anode chunk and a gas distributor. The heat-dissipating device has a thermal transfer plate and a first thermal side sheet. The thermal transfer plate has a top, a protrusion and an annular disrupting recess. The protrusion is formed at the top of the thermal transfer plate. The disrupting recess is radially formed around the protrusion. The first thermal side sheet surrounds the protrusion. The gas distributor is mounted securely in the protrusion. Because the protrusion is located between the gas distributor and the first thermal side sheet and the disrupting recess is radially formed around the protrusion, accumulated ions, molecules and deposition film particles are longitudinally disrupted and do not form a short circuit between the gas distributor and the first thermal side sheet.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 19, 2012
    Inventors: Tsai-Cheng WANG, Chin-Chung YANG, An-Ting HSIAO, Yu-Li TSAI