Patents by Inventor Yu Liang

Yu Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996323
    Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu, Ching-Yu Yang
  • Patent number: 11991497
    Abstract: An acoustic device includes a first sound producing component and a back cavity structure. The first sound producing component has a first front side and a first back side, wherein the first sound producing component is a high frequency sound unit, and the first front side faces a sound propagating opening of the acoustic device. The back cavity structure is connected to the first back side of the first sound producing component. The first sound producing component produces a first acoustic wave from the first front side towards the sound propagating opening, and the first sound producing component produces a second acoustic wave from the first back side towards a back cavity of the back cavity structure. The back cavity structure is configured to flatten a peak or a dip of a frequency response of the first sound producing component.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: May 21, 2024
    Assignee: xMEMS Labs, Inc.
    Inventors: Chao-Yu Chen, Chiung C. Lo, Jemm Yue Liang, Wen-Chien Chen, Jye Ren
  • Patent number: 11986800
    Abstract: The invention relates to a composition containing a catalyst having high catalytic stability for conducting oxidative coupling of methane (OCM) at high carbon efficiency, while improving both methane and oxygen conversion. Particularly, the inventive catalyst is a metal oxide supported catalyst, which contains an alkali metal promoter and a mixed metal oxide component having at least one alkali earth metal and at least one rare earth metal. The metal oxide support is selected in a manner, such that at least a portion of the metal oxide support is capable of reacting with at least a part or whole of the alkali metal promoter under conditions of calcination during catalyst preparation. The invention further provides a method for preparing such a metal oxide supported catalyst composition, using a calcination process. Additionally, the invention further describes a process for producing C2+ hydrocarbons, using such a catalyst composition.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: May 21, 2024
    Assignee: SABIC GLOBAL TECHNOLOGIES, B.V.
    Inventors: Wugeng Liang, Dick Nagaki, Yu-Lun Fang, David West
  • Publication number: 20240158947
    Abstract: Disclosed are a method and a device for preparing a single-crystal cladding. The method may include preparing an amorphous material; melting the amorphous material to form an amorphous melt; submerging an optical fiber in the amorphous melt; forming an amorphous cladding around a periphery of the optical fiber; and obtaining the single-crystal cladding by performing a crystallization process on the amorphous cladding. The device may include an amorphous material preparation component configured to prepare an amorphous material; an amorphous cladding preparation component configured to melt the amorphous material to form an amorphous melt, submerge an optical fiber in the amorphous melt, and form an amorphous cladding around a periphery of the optical fiber based on the amorphous melt and the optical fiber; and a single-crystal cladding preparation assembly configured to perform a crystallization process on the amorphous cladding to obtain a single-crystal cladding.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 16, 2024
    Applicant: MEISHAN BOYA ADVANCED MATERIALS CO., LTD.
    Inventors: Yu WANG, Peng GU, Zhenxing LIANG
  • Patent number: 11980714
    Abstract: An improved system and method of determining a low water and/or water-out condition in a humidifier chamber of a respiratory or surgical humidifier system can use a specific frequency band to detect changes in a temperature of a heater plate. The temperature changes can correlate to the specific heat capacity value of the humidifier chamber. The low water and/or water-out detection process can be performed without having to determine the gases flow rate and/or can be run continuously. A heater plate assembly of the system can include a compliant insulation sheet to improve thermal coupling between the heating element and the top heating plate of the heater plate assembly, thereby improving the low water and/or water-out detection process.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 14, 2024
    Assignee: Fisher & Paykel Healthcare Limited
    Inventors: Bhuvan Garg, Francis Glynn, Stephen David Evans, Wenjie Robin Liang, Yintao Yu, Logan Ross Andrew
  • Patent number: 11982014
    Abstract: The present disclosure provides an apparatus for crystal growth. The apparatus may include a furnace chamber a temperature field device placed at least partially into the furnace chamber. The furnace chamber may be a non-closed structure, and the temperature field device may be sealed.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: May 14, 2024
    Assignee: MEISHAN BOYA ADVANCED MATERIALS CO., LTD.
    Inventors: Yu Wang, Weiming Guan, Zhenxing Liang
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20240152485
    Abstract: This application provides a data switching apparatus and a data switching method. The data switching apparatus includes a plurality of dies, the plurality of dies include a plurality of die sets. Each die in the plurality of die sets is coupled to a die in a same die set and a die in a different die set through corresponding interfaces.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Yu Liang, Renjie Qu, Ke Zhang, Yan Zhao, Wan Lam
  • Publication number: 20240150928
    Abstract: The present disclosure provides a temperature field device for crystal growth. The temperature field device may include a drum; a filler filled in the drum and configured to support a crucible; a bottom plate mounted on a bottom of the temperature field device and covering a bottom end of the drum; and a cover plate mounted on a top of the temperature filed device and covering a top end of the drum.
    Type: Application
    Filed: January 14, 2024
    Publication date: May 9, 2024
    Applicant: MEISHAN BOYA ADVANCED MATERIALS CO., LTD.
    Inventors: Yu WANG, Weiming GUAN, Zhenxing LIANG
  • Publication number: 20240153897
    Abstract: A method of forming a semiconductor device according to the present disclosure includes forming a metal-insulator-metal (MIM) structure in a substrate and forming an interconnect structure over the substrate. The MIM structure includes first electrodes of a first polarity and second electrodes of a second polarity. The interconnect structure includes conductive paths electrically connecting to the first and second electrodes. The conductive paths are isolated from each other inside the interconnect structure. The method also includes forming first and second contact pads over the interconnect structure. The first contact pad electrically connects a first portion of the conductive paths corresponding to the first electrodes. The second contact pad electrically connects a second portion of the conductive paths corresponding to the second electrodes.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Fu-Chiang Kuo, Yu-Hsin Fang, Hsin-Liang Chen
  • Patent number: 11977532
    Abstract: Aggregated log index-based log record identification is provided by maintaining log files of a database system on a plurality log storage devices, the log files including log records of changes to database objects, indexing the log files to obtain a collection of log indexes, where the indexing includes, for each log storage device, indexing log records stored on the log storage device to obtain a respective log index, then based on a request, identifying log storage devices that store log records for servicing the request, the log storage devices storing log indexes, of the collection of log indexes, that index an aggregate set of log records on the log storage devices, obtaining the log indexes from the log storage devices, and aggregating the log indexes to provide an aggregated log index that provides an index of the aggregate set of log records on the log storage devices.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: May 7, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ping Liang, Xiao Feng Meng, Xue Bin Cong, Yu He
  • Publication number: 20240145302
    Abstract: A semiconductor device and a method for manufacturing an interconnecting metal layer thereof are provided. The semiconductor device includes a gate layer, a dielectric layer, an insulating layer, an epitaxial layer, and a sidewall liner. The dielectric layer is disposed on one side of the gate layer, the insulating layer is disposed on another side of the gate layer, the epitaxial layer is located on the insulating layer, and the sidewall liner penetrates the dielectric layer and the gate layer, and one end of the sidewall liner is connected to the epitaxial layer. The sidewall liner is converted from a high-k material to a low-k material by hydrogen and oxygen plasma treatments.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Shien SHIAH, Bor Chiuan HSIEH, Tsai-Jung HO, Meng-Ku CHEN, Tze-Liang LEE
  • Publication number: 20240145561
    Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Inventors: Yu-Ting TSAI, Chung-Liang CHENG, Hong-Ming LO, Chun-Chih LIN, Chyi-Tsong NI
  • Publication number: 20240147139
    Abstract: An acoustic device includes a first sound producing component and a back cavity structure. The first sound producing component has a first front side and a first back side, wherein the first sound producing component is a high frequency sound unit, and the first front side faces a sound propagating opening of the acoustic device. The back cavity structure is connected to the first back side of the first sound producing component. The first sound producing component produces a first acoustic wave from the first front side towards the sound propagating opening, and the first sound producing component produces a second acoustic wave from the first back side towards a back cavity of the back cavity structure. The back cavity structure is configured to flatten a peak or a dip of a frequency response of the first sound producing component.
    Type: Application
    Filed: June 16, 2023
    Publication date: May 2, 2024
    Applicant: xMEMS Labs, Inc.
    Inventors: Chao-Yu Chen, Chiung C. Lo, Jemm Yue Liang, Wen-Chien Chen, Jye Ren
  • Publication number: 20240145342
    Abstract: In an embodiment, a package includes an encapsulant laterally surrounding a first integrated circuit device and a second integrated circuit device, wherein the first integrated circuit device includes a die and a heat dissipation structure over the die; a sealant disposed over the heat dissipation structure; an adhesive disposed over the second integrated circuit device; and a lid disposed over the sealant and the adhesive, wherein the lid includes a first cooling passage and a second cooling passage, the first cooling passage including an opening at a bottom of the lid and aligned to the heat dissipation structure, the second cooling passage including channels aligned to the second integrated circuit device and being distant from the bottom of the lid.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 2, 2024
    Inventors: Tung-Liang Shao, You-Rong Shaw, Yu-Sheng Huang, Chen-Hua Yu
  • Patent number: 11973038
    Abstract: A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.
    Type: Grant
    Filed: August 15, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Patent number: 11971836
    Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: April 30, 2024
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Yao Zhang, Shaoli Liu, Jun Liang, Yu Chen
  • Patent number: 11972956
    Abstract: A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
  • Patent number: 11973148
    Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Ying Wu, Yung-Hsiang Chen, Yu-Lung Yeh, Yen-Hsiu Chen, Wei-Liang Chen, Ying-Tsang Ho
  • Patent number: D1027814
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: May 21, 2024
    Inventors: Yu Jing, Lin Tan, Wenlan Liang, Kun Zhang