Patents by Inventor YU-LUN HSIEH

YU-LUN HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996400
    Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. Top packages are mounted on a top side of a reconstructed wafer over a flexible tape, where conductive bumps at a bottom side of the reconstructed wafer is attached to the flexible tape, and during the mounting, a shape geometry of the respective conductive bump changes and at least a lower portion of the respective conductive bump is embraced by the flexible tape. The flexible tape is released from the conductive bumps after the mounting.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-Shuan Chung
  • Patent number: 11990295
    Abstract: An illuminated keyswitch includes a keycap, a pair of frames adapted to support the keycap in an up-down movement, the pair of frames disposed corresponding to each other and substantially rotatably coupled to each other to define an inner space under the keycap, a pair of elastic members connecting the pair of frames to be located at two opposite sides of the inner space, respectively, and an illumination light source disposed between the pair of elastic members in the inner space and adapted to provide an illumination light. During the up-down movement of the keycap, a vertical projection of the pair of frames surrounds the inner space without interfering therewith, so the illumination light passes the inner space to illuminate the keycap.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 21, 2024
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Chen Yang, Ling-Hsi Chao, Shao-Lun Hsiao, Yu-Chun Hsieh
  • Patent number: 11978598
    Abstract: A keyswitch structure includes a base, a keycap, a lift mechanism and a light-emitting part. The lift mechanism includes a first support, a second support, and a spring structure. The first support and the second support are connected to and between the base and the keycap, so that the keycap can move relative to the base in a vertical direction. The spring structure is a single structural part and is connected to the first support and the second support and drives the first support and the second support to lift the keycap in the vertical direction. The lift mechanism as a whole defines a central space that extends through the whole lift mechanism in the vertical direction. The spring structure does not enter the central space. The light-emitting part is disposed on the base corresponding to the central zone, and emits light to illuminate the keycap.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: May 7, 2024
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Chen Yang, Ling-Hsi Chao, Shao-Lun Hsiao, Yu-Chun Hsieh
  • Publication number: 20240105401
    Abstract: A keyswitch structure includes a casing, a first support, a second support, and a pressing stem. The casing forms an accommodating space and an opening communicating with the accommodating space. The first and second supports are disposed in the accommodating space and are directly and rotatably connected with the casing; the supports are also pivotally connected with each other. The pressing stem extends into the accommodating space to be rotatably connected with the first and second supports and protrudes from the casing through the opening. The pressing stem is movable parallel to a vertical direction relative to the casing through the first and second supports. A motion of the pressing stem in the vertical direction has a top dead center and a bottom dead center. When the pressing stem is at the top dead center and the bottom dead center, it does not touch the casing in the vertical direction.
    Type: Application
    Filed: July 18, 2023
    Publication date: March 28, 2024
    Applicant: DARFON ELECTRONICS CORP.
    Inventors: Yu-Chun Hsieh, Ling-Hsi Chao, Shao-Lun Hsiao, Chen Yang
  • Patent number: 11923159
    Abstract: A keyswitch structure includes a keycap support mechanism and a keycap that is supported by the keycap support mechanism in a vertical direction. The keycap support mechanism includes a base and two supports. The base has two sliding slots. Each sliding slot has an opening in a horizontal direction and an obstruction block at the opening. The horizontal direction is perpendicular to the vertical direction. Each support has a sliding portion and a linkage portion. The sliding portions slide parallel to the horizontal direction in the sliding slots correspondingly. The obstruction block prevents the corresponding sliding portion from disengaging from the corresponding sliding slot. The two linkage portions push against each other in line contact, so that the two supports are mutually driven through the two linkage portions.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: March 5, 2024
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Chen Yang, Ling-Hsi Chao, Shao-Lun Hsiao, Yu-Chun Hsieh
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 11619753
    Abstract: The disclosure provides a processing circuit adapted to read out a sensing voltage of an X-ray sensor and a signal processing method of a sampling circuit. The processing circuit includes an amplifier and the sampling circuit. An inverting input terminal of the amplifier is coupled to the X-ray sensor. The sampling circuit is coupled to an output terminal of the amplifier. The sampling circuit obtains a first voltage, a second voltage, and a sampling voltage of the X-ray sensor in different periods. The sampling voltage is between the first voltage and the second voltage. In the readout period, the sampling circuit subtracts the second voltage from the sampling voltage to obtain a third voltage, subtracts the second voltage from the first voltage to obtain a fourth voltage, and divides the third voltage by the fourth voltage to read out the sensing voltage of the X-ray sensor.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: April 4, 2023
    Assignees: InnoCare Optoelectronics Corporation, National Yang Ming Chiao Tung University
    Inventors: Zhi-Hong Wang, Hsin-Hung Lin, Chih-Hao Wu, Yu-Lun Hsieh, Ya-Hsiang Tai, Cheng Che Tu
  • Publication number: 20220026591
    Abstract: The disclosure provides a processing circuit adapted to read out a sensing voltage of an X-ray sensor and a signal processing method of a sampling circuit. The processing circuit includes an amplifier and the sampling circuit. An inverting input terminal of the amplifier is coupled to the X-ray sensor. The sampling circuit is coupled to an output terminal of the amplifier. The sampling circuit obtains a first voltage, a second voltage, and a sampling voltage of the X-ray sensor in different periods. The sampling voltage is between the first voltage and the second voltage. In the readout period, the sampling circuit subtracts the second voltage from the sampling voltage to obtain a third voltage, subtracts the second voltage from the first voltage to obtain a fourth voltage, and divides the third voltage by the fourth voltage to read out the sensing voltage of the X-ray sensor.
    Type: Application
    Filed: June 28, 2021
    Publication date: January 27, 2022
    Applicants: InnoCare Optoelectronics Corporation, National Yang Ming Chiao Tung University
    Inventors: Zhi-Hong Wang, Hsin-Hung Lin, Chih-Hao Wu, Yu-Lun Hsieh, Ya-Hsiang Tai, Cheng Che Tu
  • Patent number: 9899587
    Abstract: A lead frame for an LED package includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes separated first and second connecting surfaces. Top surfaces of the bonding electrode, the first connecting electrode, and the second connecting electrode are exposed, and support and electrically connect with light emitting chips. LED packages can be mounted on the lead frame and electrically connect with each other. The conductive layout of the lead frame further permits installation of a zener diode which can be connected to the LED packages in series or in parallel.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 20, 2018
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Yau-Tzu Jang, Yu-Liang Huang, Wen-Liang Tseng, Pin-Chuan Chen, Lung-Hsin Chen, Hsing-Fen Lo, Chao-Hsiung Chang, Che-Hsang Huang, Yu-Lun Hsieh
  • Publication number: 20170162477
    Abstract: A lead frame for an LED package includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes separated first and second connecting surfaces. Top surfaces of the bonding electrode, the first connecting electrode, and the second connecting electrode are exposed, and support and electrically connect with light emitting chips. LED packages can be mounted on the lead frame and electrically connect with each other. The conductive layout of the lead frame further permits installation of a zener diode which can be connected to the LED packages in series or in parallel.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: YAU-TZU JANG, YU-LIANG HUANG, WEN-LIANG TSENG, PIN-CHUAN CHEN, LUNG-HSIN CHEN, HSING-FEN LO, CHAO-HSIUNG CHANG, CHE-HSANG HUANG, YU-LUN HSIEH
  • Patent number: 9620692
    Abstract: An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: April 11, 2017
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Yau-Tzu Jang, Yu-Liang Huang, Wen-Liang Tseng, Pin-Chuan Chen, Lung-Hsin Chen, Hsing-Fen Lo, Chao-Hsiung Chang, Che-Hsang Huang, Yu-Lun Hsieh
  • Publication number: 20160027983
    Abstract: An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way.
    Type: Application
    Filed: October 7, 2015
    Publication date: January 28, 2016
    Inventors: YAU-TZU JANG, YU-LIANG HUANG, WEN-LIANG TSENG, PIN-CHUAN CHEN, LUNG-HSIN CHEN, HSING-FEN LO, CHAO-HSIUNG CHANG, CHE-HSANG HUANG, YU-LUN HSIEH
  • Patent number: 9184358
    Abstract: An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: November 10, 2015
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Yau-Tzu Jang, Yu-Liang Huang, Wen-Liang Tseng, Pin-Chuan Chen, Lung-Hsin Chen, Hsing-Fen Lo, Chao-Hsiung Chang, Che-Hsang Huang, Yu-Lun Hsieh
  • Patent number: 8835958
    Abstract: An LED package includes a substrate, two electrodes, an LED die and a lens. The substrate includes a top surface, a bottom surface, a plurality of side surfaces interconnecting the top surface with the bottom surface, and two opposite notches depressed downward from lateral peripheral portions of the top surface. The two electrodes penetrate through the substrate, and each of the two electrodes is exposed at both the top surface and the bottom surface of the substrate. The LED die is arranged on the substrate and electrically connected to the two electrodes. The lens is arranged on the substrate and covers the LED die. The lens includes a contacting surface adjoining the top surface of the substrate, and two protrusions extending from lateral peripheral portions of the contacting surface and respectively embedded in the two notches.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 16, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventor: Yu-Lun Hsieh
  • Publication number: 20140167078
    Abstract: An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way.
    Type: Application
    Filed: October 22, 2013
    Publication date: June 19, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: YAU-TZU JANG, YU-LIANG HUANG, WEN-LIANG TSENG, PIN-CHUAN CHEN, LUNG-HSIN CHEN, HSING-FEN LO, CHAO-HSIUNG CHANG, CHE-HSANG HUANG, YU-LUN HSIEH
  • Publication number: 20130161672
    Abstract: An LED package includes a substrate, two electrodes, an LED die and a lens. The substrate includes a top surface, a bottom surface, a plurality of side surfaces interconnecting the top surface with the bottom surface, and two opposite notches depressed downward from lateral peripheral portions of the top surface. The two electrodes penetrate through the substrate, and each of the two electrodes is exposed at both the top surface and the bottom surface of the substrate. The LED die is arranged on the substrate and electrically connected to the two electrodes. The lens is arranged on the substrate and covers the LED die. The lens includes a contacting surface adjoining the top surface of the substrate, and two protrusions extending from lateral peripheral portions of the contacting surface and respectively embedded in the two notches.
    Type: Application
    Filed: August 30, 2012
    Publication date: June 27, 2013
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventor: YU-LUN HSIEH