Abstract: An IC structure includes a first standard cell having a first pFET and a first nFET integrated; a first, second and third gates longitudinally oriented along a first direction and configured in the first standard cell; a first gate contact landing on the first gate and being adjacent two S/D contacts on two opposite edges of the first gate; a second gate contact landing on the second gate and being adjacent a single S/D contact on one edge of the second gate; and a third gate contact landing on the third gate and being free from any S/D contact. The first, second and third gate contacts span a first dimension D1, a second dimension D2, and a third dimension D3, respectively, along a second direction being orthogonal to the first direction. D1 is less than D2 and D2 is less than D3.

Abstract: An exemplary method includes receiving a device layout for a standard cell that includes a transistor and a multilayer interconnect. The multilayer interconnect includes a power line, signal lines, a source contact connected to the power line and a source of the transistor, and a drain contact connected to one of the signal lines and a drain of the transistor. The method includes modifying the device layout for the standard cell. For example, if performance of the standard cell is sensitive to power-related features, the method includes enlarging the power line and the source contact and shrinking the signal lines and the drain contact. If performance of the standard cell is sensitive to signal-related features, the method includes shrinking the power line and the source contact and enlarging the signal lines and the drain contact. A cell height of the standard cell is the same after modifying the device layout.

Abstract: A structure includes first and second cells next to each other and having first and second cell heights, respectively, along a column direction. Each cell includes at least one semiconductor active region extending lengthwise along a row direction perpendicular to the column direction. The structure further includes an array of metal tracks over the first and second cells. The metal tracks are formed by a photolithography process having a half-pitch resolution Rrow in the row direction. A first pitch of the metal tracks along the row direction is greater than or equal to 2Rrow. At least three rows of the metal tracks are in an area that is directly above the first and second cells and has a height equal to a sum of the first and second cell heights. A row of the metal tracks is disposed across a cell boundary of the first and second cells.

Abstract: An integrated circuit includes a first cell, a second cell, a buffer zone and a first power rail. The first cell includes a first set of fins extending in a first direction. Each fin of the first set of fins corresponds to a transistor of a first set of transistors. The second cell includes a second set of fins extending in the first direction. Each fin of the second set of fins corresponds to a transistor of a second set of transistors. The second set of fins is separated from the first set of fins in a second direction. The buffer zone is between the first cell and the second cell. The first power rail extends in the first direction, and overlaps at least the buffer zone. The first power rail is in a first metal layer, and is configured to supply a first voltage.

Abstract: A method performed by a computing system includes receiving a circuit design, the circuit design comprising a plurality of non-contiguous doped wells within a substrate and a plurality of resistor elements positioned above the plurality of non-contiguous doped wells such that each of the resistor elements is positioned above a different one of the plurality of non-contiguous doped wells and simulating performance of the circuit design with a first voltage applied to a first one of the plurality of resistor elements and a second voltage simultaneously applied to a second one of the plurality of resistor elements, the second voltage being different than the first voltage.

Abstract: A semiconductor device includes a substrate, a dielectric layer over the substrate, a first resistor element embedded within the dielectric layer, a second resistor element embedded within the dielectric layer, a first doped well within the substrate, the first doped well being aligned with the first resistor element, and a second doped well within the substrate, the second doped well being aligned with the second resistor element, the second doped well being non-contiguous with the first doped well.

Abstract: A method performed by a computing system includes receiving a circuit design, the circuit design comprising a plurality of non-contiguous doped wells within a substrate and a plurality of resistor elements positioned above the plurality of non-contiguous doped wells such that each of the resistor elements is positioned above a different one of the plurality of non-contiguous doped wells and simulating performance of the circuit design with a first voltage applied to a first one of the plurality of resistor elements and a second voltage simultaneously applied to a second one of the plurality of resistor elements, the second voltage being different than the first voltage.

Abstract: A method for fabricating a semiconductor device includes providing a substrate, forming a first doped well within the substrate, and forming a second doped well within the substrate. The second doped well is non-contiguous with the first doped well. The method further includes depositing a dielectric layer over the substrate, and forming a first resistor element within the dielectric layer. The first resistor element is aligned with the first doped well. The method further includes forming a second resistor element within the dielectric layer. The second resistor element being aligned with the second doped well.

Abstract: A method for fabricating a semiconductor device includes providing a substrate, forming a first doped well within the substrate, and forming a second doped well within the substrate. The second doped well is non-contiguous with the first doped well. The method further includes depositing a dielectric layer over the substrate, and forming a first resistor element within the dielectric layer. The first resistor element is aligned with the first doped well. The method further includes forming a second resistor element within the dielectric layer. The second resistor element being aligned with the second doped well.

Abstract: A semiconductor device includes a substrate, a dielectric layer over the substrate, a first resistor element embedded within the dielectric layer, a second resistor element embedded within the dielectric layer, a first doped well within the substrate, the first doped well being aligned with the first resistor element, and a second doped well within the substrate, the second doped well being aligned with the second resistor element, the second doped well being non-contiguous with the first doped well.

Abstract: A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 ?m?1.

Abstract: A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 ?m-1.

Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.

Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.

Abstract: A displacement measuring device includes a body which is movable on a plurality of rails and driven by a first shaft. An extension portion is connected to the body and a second shaft connected to the body extends through the extension portion. A first gear and a second gear are respectively mounted to the first shaft and the second shaft. Both of the two gears are engaged with a rack. A spring is received in the extension portion and pushes the second gear so that the second gear is pushed toward the rack. The second gear is snugly engaged with the rack so that the tolerance therebetween is reduced. A counting member is connected to the second shaft so that the number of the revolution of the second gear is counted and the sum of the displacement of the object can be precisely calculated.