Patents by Inventor Yu-Ming Chiu
Yu-Ming Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162094Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.Type: ApplicationFiled: January 5, 2024Publication date: May 16, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chuan CHIU, Jia-Chuan YOU, Chia-Hao CHANG, Chun-Yuan CHEN, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
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Publication number: 20240155807Abstract: A two-phase immersion-type heat dissipation structure having acute-angle notched structures is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fin surface is connected with the fins. More than half of the fins are functional fins, and at least one side surface of each of the functional fins has first and second surfaces defined thereon and connected to each other. An angle between the first surface and the fin surface is from 80 degrees to 100 degrees, and an angle between the second surface and the fin surface is less than 75 degrees.Type: ApplicationFiled: November 4, 2022Publication date: May 9, 2024Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
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Publication number: 20240155808Abstract: A two-phase immersion-cooling heat-dissipation composite structure is provided. The heat-dissipation composite structure includes a heat dissipation base, a plurality of high-thermal-conductivity fins, and at least one high-porosity solid structure. The heat dissipation base has a first surface and a second surface that face away from each other. The second surface of the heat dissipation base is in contact with a heating element immersed in a two-phase coolant. The first surface of the heat dissipation base is connected to the high-thermal-conductivity fins. The at least one high-porosity solid structure is located at the first surface of the heat dissipation base, and is connected and alternately arranged between side walls of two adjacent ones of the high-thermal-conductivity fins. Each of the high-porosity solid structure includes a plurality of closed holes and a plurality of open holes.Type: ApplicationFiled: November 4, 2022Publication date: May 9, 2024Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
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Publication number: 20240155809Abstract: A two-phase immersion-type heat dissipation structure having fins for facilitating bubble generation is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fin surface is connected with the plurality of fins. More than half of the fins are functional fins, and at least one side surface of each of the functional fins and the fin surface have an included angle therebetween that is from 80 degrees to 100 degrees. A center line average roughness (Ra) of the side surface is less than 3 ?m, and a ten-point average roughness (Rz) of the side surface is not less than 12 ?m.Type: ApplicationFiled: November 6, 2022Publication date: May 9, 2024Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
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Publication number: 20240142181Abstract: A two-phase immersion-type heat dissipation structure having skived fin with high porosity is provided. The two-phase immersion-type heat dissipation structure having skived fin with high porosity includes a porous heat dissipation structure having a total porosity that is equal to or greater than 5%. The porous heat dissipation structure includes a porous substrate and a plurality of porous and skived fins. The porous substrate has a first surface and a second surface that face away from each other. The second surface of the porous substrate is configured to be in contact with a heating element that is immersed in a two-phase coolant. The plurality of porous and skived fins are integrally formed on the first surface of the porous substrate by skiving. A first porosity of the plurality of porous and skived fins is greater than a second porosity of the porous substrate.Type: ApplicationFiled: October 27, 2022Publication date: May 2, 2024Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
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Patent number: 11961768Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.Type: GrantFiled: May 5, 2023Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
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Publication number: 20240096961Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Shih-Chuan CHIU, Tien-Lu LIN, Yu-Ming LIN, Chia-Hao CHANG, Chih-Hao WANG, Jia-Chuan YOU
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Publication number: 20240071954Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20240071953Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Patent number: 11916155Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.Type: GrantFiled: May 21, 2021Date of Patent: February 27, 2024Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
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Patent number: 8579645Abstract: A connector mechanism for connecting a board card is disclosed. The connector mechanism includes a circuit board, and a connector installed on the circuit board. An end of the board card is for inserting into the connector. The connector mechanism further includes a socket installed on the circuit board and located on a side of the connector, a rotating component pivoted to the socket, and at least one connecting component slidably installed on the rotating component and coupled to the circuit board for contacting with the other end of the board card so as to electrically connect to the board card as the end of the board card is inserted into the connector and the rotating component rotates to a connection position.Type: GrantFiled: March 27, 2012Date of Patent: November 12, 2013Assignee: Wistron CorporationInventors: Kuo-Jung Wang, Chih-Chin Yang, Yu-Ming Chiu, Chun-Lung Hsiao, Ming-Chen Chiu, Jen-Hao Liu
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Publication number: 20120289066Abstract: A connector mechanism for connecting a board card is disclosed. The connector mechanism includes a circuit board, and a connector installed on the circuit board. An end of the board card is for inserting into the connector. The connector mechanism further includes a socket installed on the circuit board and located on a side of the connector, a rotating component pivoted to the socket, and at least one connecting component sliably installed on the rotating component and coupled to the circuit board for contacting with the other end of the board card so as to electrically connect to the board card as the end of the board card is inserted into the connector and the rotating component rotates to a connection position.Type: ApplicationFiled: March 27, 2012Publication date: November 15, 2012Inventors: Kuo-Jung Wang, Chih-Chin Yang, Yu-Ming Chiu, Chun-Lung Hsiao, Ming-Chen Chiu, Jen-Hao Liu